Germanium Based Field-Effect Transistors: Challenges and Opportunities
TL;DR: This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack.
Abstract: The performance of strained silicon (Si) as the channel material for today's metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.
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TL;DR: In this article, a review of the high-K gate stack is presented, including the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging.
Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.
512 citations
TL;DR: An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the cVD h-BN film depended significantly on the film growth mode and the resultant film quality.
Abstract: Two different growth modes of large-area hexagonal boron nitride (h-BN) film, a conventional chemical vapor deposition (CVD) growth mode and a high-pressure CVD growth mode, were compared as a function of the precursor partial pressure. Conventional self-limited CVD growth was obtained below a critical partial pressure of the borazine precursor, whereas a thick h-BN layer (thicker than a critical thickness of 10 nm) was grown beyond a critical partial pressure. An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the CVD h-BN film depended significantly on the film growth mode and the resultant film quality.
116 citations
TL;DR: Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.
Abstract: Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element...
73 citations
TL;DR: Ion implantation followed by rear side flash-lamp annealing (r-FLA) is used for the fabrication of heavily doped n-type Ge with high mobility, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
Abstract: A key milestone for the next generation of high-performance multifunctional microelectronic devices is the monolithic integration of high-mobility materials with Si technology. The use of Ge instead of Si as a basic material in nanoelectronics would need homogeneous p- and n-type doping with high carrier densities. Here we use ion implantation followed by rear side flash-lamp annealing (r-FLA) for the fabrication of heavily doped n-type Ge with high mobility. This approach, in contrast to conventional annealing procedures, leads to the full recrystallization of Ge films and high P activation. In this way single crystalline Ge thin films free of defects with maximum attained carrier concentrations of 2.20 ± 0.11 × 1020 cm−3 and carrier mobilities above 260 cm2/(V·s) were obtained. The obtained ultra-doped Ge films display a room-temperature plasma frequency above 1,850 cm−1, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
65 citations
TL;DR: In this paper, the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic).
Abstract: Electronics that conform to 3D surfaces are attracting wider attention from both academia and industry. The research in the field has, thus far, focused primarily on showcasing the efficacy of various materials and fabrication methods for electronic/sensing devices on flexible substrates. As the device response changes are bound to change with stresses induced by bending, the next step will be to develop the capacity to predict the response of flexible systems under various bending conditions. This paper comprehensively reviews the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic). The discussion also includes variations in the device response due to crystal orientation, applied mechanics, band structure, and fabrication processes. Further, strategies for compensating or minimizing these bending-induced variations have been presented. Following the in-depth analysis, this paper proposes new mathematical relations to simulate and predict the device response under various bending conditions. These mathematical relations have also been used to develop new compact models that have been verified by comparing simulation results with the experimental values reported in the recent literature. These advances will enable next generation computer-aided-design tools to meet the future design needs in flexible electronics.
49 citations
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TL;DR: In this paper, a new interface engineering scheme of using both effective pre-gate surface GeO2 passivation and post-gate dielectric (postgate) treatment incorporating fluorine (F) into a high-k/germanium (Ge) gate stack was proposed.
Abstract: High-k/germanium (Ge) interfaces are significantly improved through a new interface engineering scheme of using both effective pregate surface GeO2 passivation and postgate dielectric (postgate) treatment incorporating fluorine (F) into a high-k/Ge gate stack. Capacitance-voltage (C-V) characteristics are significantly improved with minimum density of interface states (Dit) of 2 times 1011 cm-2 ldr eV-1 for Ge MOS capacitors. A hole mobility up to 396 cm2/V ldr s is achieved for Ge p-metal-oxide-semiconductor field-effect transistors (pMOSFETs) with equivalent oxide thickness that is ~10 Aring and gate leakage current density that is less than 10-3 A/cm2 at Vt plusmn 1 V. A high drain current of 37.8 muA/mum at Vg - Vt = Vd = -1.2 V is presented for a channel length of 10 mum. The Ge MOSFET interface properties are further investigated using the variable-rise-and-fall-time charge-pumping method. Over three times Dit reduction in both upper and lower halves of the Ge bandgap is observed with F incorporation, which is consistent with the observation that frequency-dependent flat voltage shift is much less for samples with F incorporation in the C-V characteristics of Ge MOS capacitors.
47 citations
TL;DR: In this paper, the growth of HfO2 thin films on (100)Ge by molecular beam epitaxy was investigated by means of transmission electron microscopy, the structural characteristics of the films grown on clean Ge surfaces are compared with those grown on passivation layers of GeOx and GeOxNy.
Abstract: We have investigated the growth of HfO2 thin films on (100)Ge by molecular beam epitaxy. By means of transmission electron microscopy, the structural characteristics of the films grown on clean Ge surfaces are compared with those grown on passivation layers of GeOx and GeOxNy. The interface was found to be very flat and thin, with an interfacial layer one or two monolayer thick. However, traces of Ge in the oxide have been detected when deposited on either one of the interfacial layers, which can be explained by the instability of the interfacial layers grown with an atomic oxygen/nitrogen beam, prior to the HfO2 deposition.
46 citations
"Germanium Based Field-Effect Transi..." refers background in this paper
...deposition (MDB) [80,81], and atomic layer deposition (ALD) (two variations: thermal [82], and plasma [83])....
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...The most common are chemical vapor deposition (CVD) [77,78], physical vapor deposition (PVD) [79], molecular beam deposition (MDB) [80,81], and atomic layer deposition (ALD) (two variations: thermal [82], and plasma [83])....
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TL;DR: Very high 2D hole gas (2DHG) drift mobility of 3100cm2∕Vs was obtained at extremely high density of 41×1011cm−2 in the modulation doped, 20nm thick, strained Ge quantum well (QW) of SiGe heterostructure at room temperature.
Abstract: Very high two-dimensional hole gas (2DHG) drift mobility of 3100cm2∕Vs is obtained at extremely high density of 41×1011cm−2 in the modulation doped, 20nm thick, strained Ge quantum well (QW) of SiGe heterostructure at room temperature. Very high 2DHG density is achieved by increasing the boron modulation doping, reducing the spacer layer thickness located between it and Ge QW, and increasing the valence-band offset of Ge QW, which also results in the enhancement of mobility. The obtained 2DHG mobility and carrier density exceed those reported for two-dimensional electron gas in the strained Si QW of SiGe heterostructures.
45 citations
TL;DR: The role of Fermi level pinning on the Schottky barrier that is often formed at the metal/semiconductor interface and common strategies for forming ohmic contacts is discussed in this paper.
Abstract: The scaling of transistors to smaller dimensions and the exploration of devices with III–V and Ge channels for digital logic places serious demands on the ohmic contacts used in these devices. Contacts with extremely low specific contact resistances are required to take full advantage of the performance promised by alternative semiconductor materials. In addition, device processes and contact morphologies must be compatible with the geometry and feature sizes of the transistors. In this article, we begin by reviewing what is known about contacts to Ge, InGaAs, InAs, and InSb, including the role of Fermi level pinning on the Schottky barrier that is often formed at the metal/semiconductor interface and common strategies for forming ohmic contacts. Then we turn our attention to the additional challenges faced when preparing ohmic contacts for the many types of field-effect transistors now under development for Ge and III–V complementary field-effect transistor technology.
44 citations
"Germanium Based Field-Effect Transi..." refers background in this paper
...For a helpful and informative review of Fermi energy pinning see [23]....
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...There are, however, significant additional engineering challenges to achieving this, such as overcoming Ge’s tendency for have a higher interface state density (Dit) near the conduction band edge [21,22] and developing low resistance ohmic contacts to n-type Ge [23,24]....
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01 Dec 2013
TL;DR: In this article, the authors demonstrate scaled, replacement gate high-k/metal gate p-channel Ge FinFETs integrated onto 300mm Si wafers for which the best device shows record peak gm, ext=2.3mS/μm.
Abstract: We demonstrate scaled, replacement gate high-k/metal gate p-channel Ge FinFETs integrated onto 300mm Si wafers for which the best device shows record peak gm, ext=2.7mS/μm (gm, int=3.3mS/μm), Q (≡gm, ext/SSsat) = 32.4 and Ion= 497μA/μm at Ioff = 100nA/μm, all at Vds= -0.5V. The high performance is a result of successful integration of oriented, highly scaled Ge fins on silicon substrates and of a low Dit gate stack with capacitance equivalent thickness=8Å. This optimized gate stack supports the highest hole mobility ever reported at sub-10Å CET. Furthermore, Ge FinFETs in the present work outperform any other reported Ge devices by more than ~2.5× (gm/SS metric) and ~2× (Ion/Ioff metric) at shortest gate lengths (down to 20nm) to the best of our knowledge.
44 citations
"Germanium Based Field-Effect Transi..." refers background or methods in this paper
...In summary, germanium based p-channel devices are beginning to show signs of readiness for production, especially in light of recent breakthroughs [200]....
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...8 nm respectively, representing a considerable breakthrough [200]....
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...Ge based FinFET technology has recently been demonstrated [69,200]....
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