Germanium Based Field-Effect Transistors: Challenges and Opportunities
TL;DR: This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack.
Abstract: The performance of strained silicon (Si) as the channel material for today's metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.
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TL;DR: In this article, a review of the high-K gate stack is presented, including the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging.
Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.
512 citations
TL;DR: An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the cVD h-BN film depended significantly on the film growth mode and the resultant film quality.
Abstract: Two different growth modes of large-area hexagonal boron nitride (h-BN) film, a conventional chemical vapor deposition (CVD) growth mode and a high-pressure CVD growth mode, were compared as a function of the precursor partial pressure. Conventional self-limited CVD growth was obtained below a critical partial pressure of the borazine precursor, whereas a thick h-BN layer (thicker than a critical thickness of 10 nm) was grown beyond a critical partial pressure. An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the CVD h-BN film depended significantly on the film growth mode and the resultant film quality.
116 citations
TL;DR: Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.
Abstract: Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element...
73 citations
TL;DR: Ion implantation followed by rear side flash-lamp annealing (r-FLA) is used for the fabrication of heavily doped n-type Ge with high mobility, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
Abstract: A key milestone for the next generation of high-performance multifunctional microelectronic devices is the monolithic integration of high-mobility materials with Si technology. The use of Ge instead of Si as a basic material in nanoelectronics would need homogeneous p- and n-type doping with high carrier densities. Here we use ion implantation followed by rear side flash-lamp annealing (r-FLA) for the fabrication of heavily doped n-type Ge with high mobility. This approach, in contrast to conventional annealing procedures, leads to the full recrystallization of Ge films and high P activation. In this way single crystalline Ge thin films free of defects with maximum attained carrier concentrations of 2.20 ± 0.11 × 1020 cm−3 and carrier mobilities above 260 cm2/(V·s) were obtained. The obtained ultra-doped Ge films display a room-temperature plasma frequency above 1,850 cm−1, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
65 citations
TL;DR: In this paper, the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic).
Abstract: Electronics that conform to 3D surfaces are attracting wider attention from both academia and industry. The research in the field has, thus far, focused primarily on showcasing the efficacy of various materials and fabrication methods for electronic/sensing devices on flexible substrates. As the device response changes are bound to change with stresses induced by bending, the next step will be to develop the capacity to predict the response of flexible systems under various bending conditions. This paper comprehensively reviews the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic). The discussion also includes variations in the device response due to crystal orientation, applied mechanics, band structure, and fabrication processes. Further, strategies for compensating or minimizing these bending-induced variations have been presented. Following the in-depth analysis, this paper proposes new mathematical relations to simulate and predict the device response under various bending conditions. These mathematical relations have also been used to develop new compact models that have been verified by comparing simulation results with the experimental values reported in the recent literature. These advances will enable next generation computer-aided-design tools to meet the future design needs in flexible electronics.
49 citations
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13 citations
"Germanium Based Field-Effect Transi..." refers background in this paper
...Other materials are also being investigated such as Y2O3 [100], TiO2 [13], and La2O3 [101]....
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...The insertion of thin potential barriers, such as that provided by thin layers of Al2O3 [146], SiN3 [147], TiO2 [145,148], ZnO [24], Ge3N4 [149], GeOx [150,151], MgO [152,153], and Y2O3 [154] have been shown to reduce the Schottky barrier height as well as facilitate the unpinning of Fermi-level in n-type Ge....
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TL;DR: In this article, the structural and band alignment properties of nanoscale titanium dioxide (TiO2) thin films deposited on epitaxial crystallographic oriented Ge layers grown on (100), (110), and (111)A GaAs substrates by molecular beam epitaxy were investigated.
Abstract: We have investigated the structural and band alignment properties of nanoscale titanium dioxide (TiO2) thin films deposited on epitaxial crystallographic oriented Ge layers grown on (100), (110), and (111)A GaAs substrates by molecular beam epitaxy. The TiO2 thin films deposited at low temperature by physical vapor deposition were found to be amorphous in nature, and high-resolution transmission electron microscopy confirmed a sharp heterointerface between the TiO2 thin film and the epitaxially grown Ge with no traceable interfacial layer. A comprehensive assessment on the effect of substrate orientation on the band alignment at the TiO2/Ge heterointerface is presented by utilizing x-ray photoelectron spectroscopy and spectroscopic ellipsometry. A band-gap of 3.33 ± 0.02 eV was determined for the amorphous TiO2 thin film from the Tauc plot. Irrespective of the crystallographic orientation of the epitaxial Ge layer, a sufficient valence band-offset of greater than 2 eV was obtained at the TiO2/Ge heterointerface while the corresponding conduction band-offsets for the aforementioned TiO2/Ge system were found to be smaller than 1 eV. A comparative assessment on the effect of Ge substrate orientation revealed a valence band-offset relation of ΔEV(100) > ΔEV(111) > ΔEV(110) and a conduction band-offset relation of ΔEC(110) > ΔEC(111) > ΔEC(100). These band-offset parameters are of critical importance and will provide key insight for the design and performance analysis of TiO2 for potential high-κ dielectric integration and for future metal-insulator-semiconductor contact applications with next generation of Ge based metal-oxide field-effect transistors.
12 citations
"Germanium Based Field-Effect Transi..." refers background in this paper
...Recently, Zhang et al. [13] demonstrated an EOT of 0.65 nm using a gate stack of TiO2/Al2O3/Ge....
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...Crystallographic-orientation agnostic TiO2-based MIS contacts may be particularly useful in the next generation of Ge FinFETs, where different Ge orientations can be exploited to facilitate mobility enhancement for n- and p-channel devices [148]....
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...The insertion of thin potential barriers, such as that provided by thin layers of Al2O3 [146], SiN3 [147], TiO2 [145,148], ZnO [24], Ge3N4 [149], GeOx [150,151], MgO [152,153], and Y2O3 [154] have been shown to reduce the Schottky barrier height as well as facilitate the unpinning of Fermi-level in n-type Ge....
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...For this work, a fair leakage current of about 1 × 10 −2 A/cm 2 at Vg = −1 V is reported for the combined TiO2/Al2O3/Ge stack....
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...It has been recently reported that the lower CBOs obtained for the crystallographic oriented TiO2/Ge system, irrespective of the Ge crystallographic orientation, presents a potential for employing a TiO2 insulating layer for MIS contact applications....
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TL;DR: In this article, a p-AlSb0.9As0.1/p-Sb/GaSb structure was used to construct a 1 μm gate-length GaSb p-channel modulation-doped field effect transistors.
Abstract: GaSb p-channel modulation-doped field-effect transistors based on a p-AlSb0.9As0.1/p-AlSb/GaSb structure have been fabricated. Transconductances as high as 50 ms/mm at room temperature and 220 to 283 ms/mm at 77 K were obtained for 1 μm gate-length devices. These 77 K transconductances represent the highest values reported for any compound p-channel heterojunction field-effect transistors.
11 citations
TL;DR: In this paper, a well-behaved Ge n-channel metal-oxide-semiconductor field effect transistors on (001) substrates with dispersion-free, high on/off ratio, and high peak mobility are demonstrated.
Abstract: Well-behaved Ge n-channel metal-oxide-semiconductor field-effect transistors on (001) substrates with dispersion-free, high on/off ratio, and high peak mobility are demonstrated. The interface trap density is effectively reduced down to 5 × 1011 cm−2 eV−1 near midgap by GeO2 passivation using rapid thermal oxidation, resulting in high peak mobility of ∼1050 cm2/Vs. The fast roll-off of the mobility at high electric field is probably due to the large surface roughness scattering. By applying uniaxial 〈110〉 tensile strain (0.08%) on 〈110〉 channel direction, the best mobility enhancement (12%) can be achieved. The calculated strain responses with proper stress configurations are consistent with experimental results.
10 citations
22 Apr 2013
TL;DR: In this article, the TaN/HfON/GeO2/n-Ge pMOSFETs were fabricated with different formation processes of GeO2 interfacial layer.
Abstract: The TaN/HfON/GeO2/n-Ge pMOSFETs were fabricated with different formation processes of GeO2 interfacial layer. Ultra low EOT of around 0.5 nm is achieved using GeO2 grown by H2O plasma together with in-situ grown HfON gate dielectric, and simultaneously the peak hole mobility of Ge pMOSFET is 312 cm2/V*s.
10 citations
"Germanium Based Field-Effect Transi..." refers background in this paper
...A wide variety of oxidation methods are being explored, including thermal oxidation [12,71,102,119–130], ozone or atomic oxygen exposure [131–136], high-pressure oxidation [103,104,137], radical oxidation [138], and plasma techniques [9,14,139]....
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