Germanium Based Field-Effect Transistors: Challenges and Opportunities
TL;DR: This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack.
Abstract: The performance of strained silicon (Si) as the channel material for today's metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.
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TL;DR: In this article, a review of the high-K gate stack is presented, including the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging.
Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.
512 citations
TL;DR: An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the cVD h-BN film depended significantly on the film growth mode and the resultant film quality.
Abstract: Two different growth modes of large-area hexagonal boron nitride (h-BN) film, a conventional chemical vapor deposition (CVD) growth mode and a high-pressure CVD growth mode, were compared as a function of the precursor partial pressure. Conventional self-limited CVD growth was obtained below a critical partial pressure of the borazine precursor, whereas a thick h-BN layer (thicker than a critical thickness of 10 nm) was grown beyond a critical partial pressure. An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the CVD h-BN film depended significantly on the film growth mode and the resultant film quality.
116 citations
TL;DR: Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.
Abstract: Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element...
73 citations
TL;DR: Ion implantation followed by rear side flash-lamp annealing (r-FLA) is used for the fabrication of heavily doped n-type Ge with high mobility, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
Abstract: A key milestone for the next generation of high-performance multifunctional microelectronic devices is the monolithic integration of high-mobility materials with Si technology. The use of Ge instead of Si as a basic material in nanoelectronics would need homogeneous p- and n-type doping with high carrier densities. Here we use ion implantation followed by rear side flash-lamp annealing (r-FLA) for the fabrication of heavily doped n-type Ge with high mobility. This approach, in contrast to conventional annealing procedures, leads to the full recrystallization of Ge films and high P activation. In this way single crystalline Ge thin films free of defects with maximum attained carrier concentrations of 2.20 ± 0.11 × 1020 cm−3 and carrier mobilities above 260 cm2/(V·s) were obtained. The obtained ultra-doped Ge films display a room-temperature plasma frequency above 1,850 cm−1, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
65 citations
TL;DR: In this paper, the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic).
Abstract: Electronics that conform to 3D surfaces are attracting wider attention from both academia and industry. The research in the field has, thus far, focused primarily on showcasing the efficacy of various materials and fabrication methods for electronic/sensing devices on flexible substrates. As the device response changes are bound to change with stresses induced by bending, the next step will be to develop the capacity to predict the response of flexible systems under various bending conditions. This paper comprehensively reviews the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic). The discussion also includes variations in the device response due to crystal orientation, applied mechanics, band structure, and fabrication processes. Further, strategies for compensating or minimizing these bending-induced variations have been presented. Following the in-depth analysis, this paper proposes new mathematical relations to simulate and predict the device response under various bending conditions. These mathematical relations have also been used to develop new compact models that have been verified by comparing simulation results with the experimental values reported in the recent literature. These advances will enable next generation computer-aided-design tools to meet the future design needs in flexible electronics.
49 citations
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23 Mar 2010-Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena
TL;DR: In this paper, carbon delta-doping is achieved by switching off group III elements while the flow of CBr4 is on during the growth of AlSb barrier layer, which decreases hole mobility of strained In0.3Ga0.7Sb/AlxGa1−xSb quantum well.
Abstract: Carbon-tetrabromide (CBr4) is utilized as the p-type doping source in modulation-doped pseudomorphic In0.3Ga0.7Sb/AlxGa1−xSb quantum well structure. Carbon delta-doping is achieved by switching off group III elements while the flow of CBr4 is on during the growth of AlSb barrier layer. The hole mobility of strained In0.3Ga0.7Sb quantum well decreases monotonically from 600 to 400 cm2/V s while the sheet carrier concentration increases from 7.5×1011 to 4.1×1012 cm−2 with increasing carbon delta-doping.
6 citations
TL;DR: In this article, the inversion-layer hole mobility in MOSFETs with thin silicon-germanium (Si1-xGex) channels grown pseudomorphically on Si is calculated using a selfconsistent 6 × 6 k ·p Poisson-Schrodinger mobility simulator calibrated to experimental and simulation data.
Abstract: The inversion-layer hole mobility in MOSFETs with thin silicon-germanium (Si1-xGex) channels grown pseudomorphically on Si is calculated using a self-consistent 6 × 6 k ·p Poisson-Schrodinger mobility simulator calibrated to experimental and simulation data. The addition of uniaxial compressive stress to the inherent biaxial compressive strain of the pseudomorphic Si1-xGex layer is found to further enhance hole mobility by up to 2.5×. Two-dimensional device simulations are used to assess the benefit of the Si1-xGex heterostructure channel for boosting the ON-state current (Ion) of p-channel MOSFETs with a gate length (Lg) of 18 nm; the results show a moderate (10%-40%) improvement over a bulk-Si MOSFET.
6 citations
27 May 2009
TL;DR: In this paper, the authors present theoretical results regarding the hole mobility in Ge, GaAs, InGaAs, Sb and GaSb p-channels with SiO 2 2 insulator.
Abstract: We present theoretical results regarding the hole mobility in Ge, GaAs, InGaAs, InSb and GaSb p-channels with SiO
2
insulator. The valence subband structure is calculated self-consistently within the framework of a six-band k .
p and finite-difference methods. Various scattering processes, non-polar (NP) phonon scattering (acoustic and optical), longitudinal-optical (LO) phonon scattering (Frohlich scattering, III-Vs only), alloy scattering (AL) (InGaAs only) and surface roughness (SR) scattering are included in the calculation. Dielectric screening effects on SR and LO scattering are also taken into account. The results show that Ge and III-V materials have great potential in enhancing hole mobility above the 'universal' Si value. The application of strain, especially uniaxial stress for Ge p-channels and biaxially compressive stress for III-V p-channels, is found to have a significant beneficial effect. Among strained p-channels, InSb yields the largest mobility enhancement. Our theoretical results will finally be compared with available experimental data.
6 citations
TL;DR: In this article, the transport properties of all carriers present can greatly aid understanding of new materials and devices, identifying processing problems, and reducing costs by identifying good material early in the fabrication process.
Abstract: Electronic transport characterization in semiconductor materials is becoming increasingly difficult as multi-layer and multi-carrier materials become more common. Examples include multiply doped or compensated regions, doping non-uniformities perpendicular to the conduction plane, 2D carriers at surfaces and interfaces, heterostructures, multiple quantum well structures, and materials with carriers populating different conduction band minima or valence band maxima. The heterostructures can contain delta-doped layers only a few atoms thick sandwiched between many other layers. Knowledge of the transport properties of all carriers present can greatly aid understanding of new materials and devices, identifying processing problems, and reducing costs by identifying good material early in the fabrication process.
5 citations
"Germanium Based Field-Effect Transi..." refers background in this paper
...An excellent review on the nature of parallel conduction can be found in [52]....
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TL;DR: In this article, tensile gates are shown to be an effective stressor on gatefirst n-FinFETs, but not on gate-last: in the latter case a slight mobility degradation is predicted.
Abstract: Novel device architectures offer improved scalability but come often at the price of increased layout sensitivity and a reduced or changed effectiveness of stressors and gate-last integration schemes. This work focuses on stress effects in n-type FinFETs and p-type Si1-xGex-channel pFETs, and relies mainly on TCAD results. It will be shown that on n-FinFETs, tensile stressed Contact EtchStop Layers (t-CESL) are less effective than on planar FETs when a gate-first scheme is used. For gate-last schemes, CESL is as effective as on planar FETs, moreover a strong boost is expected when compared to gate-first schemes. Tensile stressed gates are shown to be an effective stressor on gatefirst n-FinFETs, but not on gate-last: in the latter case a slight mobility degradation is predicted. For pFETs with strained Si1-xGex-channels like the Implant-Free Quantum Well (IFQW) FET, it will be shown that elastic relaxation during source/drain recess is an important factor that reduces the effectiveness of Si1-yGey source/drain stressors. For scaled technologies, omitting the source/drain recess altogether and opting for a raised source/drain scheme is preferred. In IFQW pFETs, dependence of the drive current on transistor width is an important concern. It will be shown that a Si1-yGey source/drain reduces the layout dependence of IFQW FETs, an effect that is enhanced further when combined with a gate-last integration scheme.
5 citations