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Journal ArticleDOI

Germanium Based Field-Effect Transistors: Challenges and Opportunities

19 Mar 2014-Materials (MDPI AG)-Vol. 7, Iss: 3, pp 2301-2339
TL;DR: This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack.
Abstract: The performance of strained silicon (Si) as the channel material for today's metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.

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Citations
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Journal ArticleDOI
TL;DR: In this article, a review of the high-K gate stack is presented, including the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging.
Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.

512 citations

Journal ArticleDOI
TL;DR: An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the cVD h-BN film depended significantly on the film growth mode and the resultant film quality.
Abstract: Two different growth modes of large-area hexagonal boron nitride (h-BN) film, a conventional chemical vapor deposition (CVD) growth mode and a high-pressure CVD growth mode, were compared as a function of the precursor partial pressure. Conventional self-limited CVD growth was obtained below a critical partial pressure of the borazine precursor, whereas a thick h-BN layer (thicker than a critical thickness of 10 nm) was grown beyond a critical partial pressure. An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the CVD h-BN film depended significantly on the film growth mode and the resultant film quality.

116 citations

Journal ArticleDOI
17 Jan 2017-ACS Nano
TL;DR: Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.
Abstract: Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element...

73 citations

Journal ArticleDOI
TL;DR: Ion implantation followed by rear side flash-lamp annealing (r-FLA) is used for the fabrication of heavily doped n-type Ge with high mobility, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
Abstract: A key milestone for the next generation of high-performance multifunctional microelectronic devices is the monolithic integration of high-mobility materials with Si technology. The use of Ge instead of Si as a basic material in nanoelectronics would need homogeneous p- and n-type doping with high carrier densities. Here we use ion implantation followed by rear side flash-lamp annealing (r-FLA) for the fabrication of heavily doped n-type Ge with high mobility. This approach, in contrast to conventional annealing procedures, leads to the full recrystallization of Ge films and high P activation. In this way single crystalline Ge thin films free of defects with maximum attained carrier concentrations of 2.20 ± 0.11 × 1020 cm−3 and carrier mobilities above 260 cm2/(V·s) were obtained. The obtained ultra-doped Ge films display a room-temperature plasma frequency above 1,850 cm−1, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.

65 citations

Journal ArticleDOI
TL;DR: In this paper, the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic).
Abstract: Electronics that conform to 3D surfaces are attracting wider attention from both academia and industry. The research in the field has, thus far, focused primarily on showcasing the efficacy of various materials and fabrication methods for electronic/sensing devices on flexible substrates. As the device response changes are bound to change with stresses induced by bending, the next step will be to develop the capacity to predict the response of flexible systems under various bending conditions. This paper comprehensively reviews the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic). The discussion also includes variations in the device response due to crystal orientation, applied mechanics, band structure, and fabrication processes. Further, strategies for compensating or minimizing these bending-induced variations have been presented. Following the in-depth analysis, this paper proposes new mathematical relations to simulate and predict the device response under various bending conditions. These mathematical relations have also been used to develop new compact models that have been verified by comparing simulation results with the experimental values reported in the recent literature. These advances will enable next generation computer-aided-design tools to meet the future design needs in flexible electronics.

49 citations

References
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Proceedings ArticleDOI
01 Dec 2008
TL;DR: In this paper, a high-speed and low-power III-V p-channel QWFET using a compressively strained InSb QW structure is described, achieving peak transconductance (Gm) of 510 muS/mum and cut-off frequency (fT) of 140 GHz at supply voltage of 0.5V.
Abstract: This paper describes for the first time, a high-speed and low-power III-V p-channel QWFET using a compressively strained InSb QW structure. The InSb p-channel QW device structure, grown using solid source MBE, demonstrates a high hole mobility of 1,230 cm2/V-s. The shortest 40 nm gate length (LG) transistors achieve peak transconductance (Gm) of 510 muS/mum and cut-off frequency (fT) of 140 GHz at supply voltage of 0.5V. These represent the highest Gm and fT ever reported for III-V p-channel FETs. In addition, effective hole velocity of this device has been measured and compared to that of the standard strained Si p-channel MOSFET.

189 citations


"Germanium Based Field-Effect Transi..." refers background in this paper

  • ...Utilizing Ge, with its lower lattice mismatch to Si (InSb is ~19% versus ~4% for Ge), as the channel material in a QWFET configuration appears to be the most attractive option for high-mobility low-power PMOS logic....

    [...]

  • ..., InSb [157,158], InGaSb [159–167], and GaSb [160,165,168–173]) are potential p-channel candidates due their high hole mobilities....

    [...]

  • ...Figure 14 compares saturation current (Idsat, also called Ion) vs. off-state leakage current (Ioff) characteristics of 65 nm Ge pMOSFET [10], 40 nm InSb QWFET [157], and 100 nm Ge MOS-QWFET [15] at supply voltage of −0.5 V....

    [...]

  • ...off-state leakage current (Ioff) characteristics of 65 nm Ge pMOSFET [10], 40 nm InSb QWFET [157], and 100 nm Ge MOS-QWFET [15] at supply voltage of −0....

    [...]

  • ...In InSb, a μh of 1230 cm 2 /Vs was reported (at Ns = 1.1 × 10 12 cm −2 with 2% strain) [157]....

    [...]

Journal ArticleDOI
TL;DR: Growth of Ge on Si(111) was mediated by a monolayer of Sb floating on the surface, and Shockley partial dislocations initially thread to the surface and then act as nucleation sites for complementary partial dislocation which glide down to the interface, leaving behind a fully relaxed, defect-free, epitaxial Ge film.
Abstract: Islanding and misfit relaxation are obstacles for growth of heteroepitaxial films. Surfactants not only inhibit islanding, but also control defect structure. Growth of Ge on Si(111) was mediated by a monolayer of Sb floating on the surface. Upon exceeding the critical thickness, Shockley partial dislocations initially thread to the surface and then act as nucleation sites for complementary partial dislocations which glide down to the interface, leaving behind a fully relaxed, defect-free, epitaxial Ge film

185 citations


"Germanium Based Field-Effect Transi..." refers methods in this paper

  • ...[55] showed that when Sb is used as the...

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Journal ArticleDOI
TL;DR: CMOS-compatible integration approaches of Ge channel devices are presented and the device design and scalability of strained-Ge buried-channel MOSFETs are discussed.
Abstract: This paper reviews progress and current critical issues with respect to the integration of germanium (Ge) surface-channel MOSFET devices as well as strained-Ge buried-channel MOSFET structures. The device design and scalability of strained-Ge buried-channel MOSFETs are discussed on the basis of our recent results. CMOS-compatible integration approaches of Ge channel devices are presented.

184 citations

Journal ArticleDOI
TL;DR: In this paper, an ultrathin interfacial silicon nitride layer was added to the metal/SiN/Ge Schottky diode to suppress strong Fermi level pinning, which resulted in effective control of Schotty barrier height.
Abstract: Schottky barrier height modulation in metal/Ge Schottky junction was demonstrated by inserting an ultrathin interfacial silicon nitride layer. The SiN interfacial layer suppressed strong Fermi level pinning in metal/Ge Schottky junction, which resulted in effective control of Schottky barrier height. Metal/SiN/Ge Schottky diode was systematically investigated in terms of SiN thickness dependence and metal work function dependence. At an optimal SiN thickness, Ohmic contact between metal and Ge was obtained as a result of Fermi level depinning, and almost ideal Schottky barrier height determined by the work function difference between the metal and Ge was achieved. This technology was finally applied to metal source/drain Ge metal-oxide-semiconductor field-effect-transistors with low source/drain resistance.

174 citations


"Germanium Based Field-Effect Transi..." refers background in this paper

  • ...The insertion of thin potential barriers, such as that provided by thin layers of Al2O3 [146], SiN3 [147], TiO2 [145,148], ZnO [24], Ge3N4 [149], GeOx [150,151], MgO [152,153], and Y2O3 [154] have been shown to reduce the Schottky barrier height as well as facilitate the unpinning of Fermi-level in n-type Ge....

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Journal ArticleDOI
TL;DR: In this article, the authors introduced ozone oxidation to engineer Ge/insulator interface and found that the interface and Dit are strongly affected by the distribution of oxidation states and the quality of the suboxide.
Abstract: Passivation of Ge has been a critical issue for Ge MOS applications in future technology nodes. In this letter, we introduce ozone oxidation to engineer Ge/insulator interface. Density of interface states (Dit) across the bandgap and close to the conduction band edge was extracted using conductance technique at low temperatures. Dit dependence on growth conditions was studied. Minimum Dit of 3 times 1011 cm-2V-1 was demonstrated. Physical quality of the interface was investigated through Ge 3d spectra measurements. We found that the interface and Dit are strongly affected by the distribution of oxidation states and the quality of the suboxide.

169 citations

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What are the challenges and opportunities in the field of Ge optics?

The provided paper does not discuss the challenges and opportunities in the field of Ge optics. The paper focuses on the challenges and opportunities of germanium-based field-effect transistors.