Germanium Based Field-Effect Transistors: Challenges and Opportunities
TL;DR: This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack.
Abstract: The performance of strained silicon (Si) as the channel material for today's metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.
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TL;DR: In this article, a review of the high-K gate stack is presented, including the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging.
Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.
512 citations
TL;DR: An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the cVD h-BN film depended significantly on the film growth mode and the resultant film quality.
Abstract: Two different growth modes of large-area hexagonal boron nitride (h-BN) film, a conventional chemical vapor deposition (CVD) growth mode and a high-pressure CVD growth mode, were compared as a function of the precursor partial pressure. Conventional self-limited CVD growth was obtained below a critical partial pressure of the borazine precursor, whereas a thick h-BN layer (thicker than a critical thickness of 10 nm) was grown beyond a critical partial pressure. An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the CVD h-BN film depended significantly on the film growth mode and the resultant film quality.
116 citations
TL;DR: Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.
Abstract: Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element...
73 citations
TL;DR: Ion implantation followed by rear side flash-lamp annealing (r-FLA) is used for the fabrication of heavily doped n-type Ge with high mobility, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
Abstract: A key milestone for the next generation of high-performance multifunctional microelectronic devices is the monolithic integration of high-mobility materials with Si technology. The use of Ge instead of Si as a basic material in nanoelectronics would need homogeneous p- and n-type doping with high carrier densities. Here we use ion implantation followed by rear side flash-lamp annealing (r-FLA) for the fabrication of heavily doped n-type Ge with high mobility. This approach, in contrast to conventional annealing procedures, leads to the full recrystallization of Ge films and high P activation. In this way single crystalline Ge thin films free of defects with maximum attained carrier concentrations of 2.20 ± 0.11 × 1020 cm−3 and carrier mobilities above 260 cm2/(V·s) were obtained. The obtained ultra-doped Ge films display a room-temperature plasma frequency above 1,850 cm−1, which enables to exploit the plasmonic properties of Ge for sensing in the mid-infrared spectral range.
65 citations
TL;DR: In this paper, the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic).
Abstract: Electronics that conform to 3D surfaces are attracting wider attention from both academia and industry. The research in the field has, thus far, focused primarily on showcasing the efficacy of various materials and fabrication methods for electronic/sensing devices on flexible substrates. As the device response changes are bound to change with stresses induced by bending, the next step will be to develop the capacity to predict the response of flexible systems under various bending conditions. This paper comprehensively reviews the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic). The discussion also includes variations in the device response due to crystal orientation, applied mechanics, band structure, and fabrication processes. Further, strategies for compensating or minimizing these bending-induced variations have been presented. Following the in-depth analysis, this paper proposes new mathematical relations to simulate and predict the device response under various bending conditions. These mathematical relations have also been used to develop new compact models that have been verified by comparing simulation results with the experimental values reported in the recent literature. These advances will enable next generation computer-aided-design tools to meet the future design needs in flexible electronics.
49 citations
References
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01 Dec 2009
TL;DR: In this article, an advanced composite high-K gate stack (4nm TaSiO x -2nm InP) in the In 0.7 Ga 0.3 As quantum-well field effect transistor (QWFET) on silicon substrate is described.
Abstract: This paper describes integration of an advanced composite high-K gate stack (4nm TaSiO x -2nm InP) in the In 0.7 Ga 0.3 As quantum-well field effect transistor (QWFET) on silicon substrate. The composite high-K gate stack enables both (i) thin electrical oxide thickness (t OXE ) and low gate leakage (J G ) and (ii) effective carrier confinement and high effective carrier velocity (V eff ) in the QW channel. The L G =75nm In 0.7 Ga 0.3 As QWFET on Si with this composite high-K gate stack achieves high transconductance of 1750µS/µm and high drive current of 0.49mA/µm at V DS =0.5V.
166 citations
"Germanium Based Field-Effect Transi..." refers background in this paper
...High-performance n-channel InGaAs quantum well field effect transistor (QWFET) on Si has been demonstrated [25,26,155,156]....
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...In order to realize a Ge QWFET configuration, high bandgap barrier layers are essential in order to (i) eliminate parallel conduction to the channel [25,26,155,156]; (ii) provide a large VBO for hole confinement; (iii) achieve a high-quality high-k/barrier interface [182–185]; (iv) control the lattice mismatch [25,186]; (v) provide strain to the active channel; (vi) give superior interface properties; and (vii) improve ohmic contacts [187,188]....
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..., excellent III-V based NMOS devices have been demonstrated [25,26], whereas a comparably...
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IBM1
TL;DR: The microstructure of Ge films grown layer by layer on Si(001) surfaces is studied, demonstrating that the so-called critical thickness has to take into account the formation energy of the strain-relieving defects (in general, dislocations), and not only the energy to move the defects, as has generally been done up to now.
Abstract: We have studied the microstructure of Ge films grown layer by layer on Si(001) surfaces. The growth mode was changed from a Stranski-Krastanov mode (layer by layer for 3 monolayers, followed by islanding) to a layer-by-layer growth mode by passivation of the surface with 1 monolayer of arsenic. This change in growth morphology results in drastic changes in the mechanism of strain relief. Unlike films grown on bare Si, these films remain pseudomorphically strained up to a thickness of about 10 monolayers. At a film thickness of 12 monolayers, we observe the catastrophic formation of strain-induced defects. These consist of several {111} planes tilted perpendicular to the substrate. The defects are ssV-shaped and, consequently, relieve the misfit progressively as the film grows. At a film thickness of 50 monolayers, we observe that the ssV-shaped defects serve as nucleation sites for dislocations that climb down into the Si substrate. These dislocations then glide through the film to relieve the misfit in previously undefected areas. Thus, the misfit is relieved partly by ssV-shaped defects located in the Ge layer and partly by edge dislocations located in the Si substrate. For thick films, we observe that most of the ssV-shaped defects have been covered by Ge oriented epitaxially with the substrate, but they have also generated twins and stacking faults that extend throughout the whole film. This work has fundamental implications for the understanding of strain relief during ``normal'' growth. Indeed, it demonstrates that the so-called critical thickness has to take into account the formation energy of the strain-relieving defects (in general, dislocations), and not only the energy to move the defects, as has generally been done up to now.
163 citations
"Germanium Based Field-Effect Transi..." refers background in this paper
...[33] found that when As is used as the surfactant during Ge on Si(100) growth it results in V-shaped defects that can generate stacking faults and twins that extend throughout the entire film....
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...In general, elastic deformation cannot accommodate all the strain and as a result, misfit dislocations nucleate at the island edges [33]....
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...As the built-in strain energy increases with increasing film thickness, there is a sudden transition from 2D to 3D growth modes, also known as island growth [33]....
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TL;DR: An ultrathin equivalent oxide thickness (EOT) Al2O3/GeOx/Ge gate stack with a superior Geox/Ge metal-oxide-semiconductor (MOS) interface and p-channel MOSFETs using this gate stack have been fabricated by a plasma post oxidation method as mentioned in this paper.
Abstract: An ultrathin equivalent oxide thickness (EOT) Al2O3/ GeOx/Ge gate stack with a superior GeOx/Ge metal-oxide-semiconductor (MOS) interface and p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) using this gate stack have been fabricated by a plasma post oxidation method. The properties of the GeOx/ Ge MOS interfaces are systemically investigated, and it is revealed that there is a universal relationship between the interface state density (Dit) at the GeOx/Ge interface and the GeOx interfacial layer thickness. Ge pMOSFETs on a (100) Ge substrate using the Al2O3/GeOx/Ge gate stack have been demonstrated with an EOT down to 0.98 nm. It is found that the Ge pMOSFETs exhibit the peak hole mobility values of 515, 466, and 401 cm2/ V·s at an EOT of 1.18, 1.06, and 0.98 nm, respectively, which has much weaker EOT dependence than the trend of the hole mobility values reported so far, because of low Dit of the present gate stack in the ultrathin EOT region of ~1 nm.
161 citations
05 Dec 2005
TL;DR: InSb quantum well transistors with unity gain cutoff frequency, fT, of 305 GHz and 256 GHz, respectively, at 05V VDS were demonstrated in this paper.
Abstract: We demonstrate for the first time 85nm gate length enhancement and depletion mode InSb quantum well transistors with unity gain cutoff frequency, fT, of 305 GHz and 256 GHz, respectively, at 05V VDS, suitable for high speed, very low power logic applications The InSb transistors demonstrate 50% higher unity gain cutoff frequency, fT, than silicon NMOS transistors while consuming 10 times less active power
161 citations
TL;DR: In this article, a model based on the charge neutrality level is proposed to explain all experimental work he performed on III-V MOSFETs using ex situ atomic-layer-deposited high-k dielectrics.
Abstract: Lacking a suitable gate insulator, practical GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) have remained all but a dream for more than four decades. The physics and chemistry of III–V compound semiconductor surfaces or interfaces are problems so complex that our understanding is still limited even after enormous research efforts. Most research is focused on surface pretreatments, oxide formation, and dielectric materials; less attention is paid to the III–V substrate itself. The purpose of this article is to show that device physics more related to III–V substrates is as important as surface chemistry for realizing high-performance III–V MOSFETs. The history and present status of III–V MOSFET research are briefly reviewed. A model based on the charge neutrality level is proposed to explain all experimental work he performed on III–V MOSFETs using ex situ atomic-layer-deposited high-k dielectrics. This model can also explain all reported experimental observations on III–V MOSFETs using ...
158 citations