Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test
06 May 2007-pp 167-172
TL;DR: The authors show that glitching activity on nodes must be considered in order to correctly handle constraints on instantaneous peak power and include a power profiler that can analyze a pattern source for violations and a PODEM-based pattern generation engine for generating power-safe patterns.
Abstract: Excessive dynamic voltage drop in the power supply rails during test mode is known to result in false failures and impact yield when testing devices that use low-cost wire-bond packages. Identifying and debugging such test failures is a complex and effort-intensive process, especially when scan compression is involved. From a design cycle-tune view point, it is best to avoid this problem by generating "power-safe" scan patterns. The generation of power-safe patterns must take into consideration the DFT architecture, physical design, tuning and power constraints. In this paper, the authors propose such a framework and show experimental results on some benchmark circuits. The framework can address a non-uniform power grid and region-based power constraints. The authors show that glitching activity on nodes must be considered in order to correctly handle constraints on instantaneous peak power. The framework includes a power profiler that can analyze a pattern source for violations and a PODEM-based pattern generation engine for generating power-safe patterns.
Citations
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25 May 2015
TL;DR: This paper proposes a novel method for identifying areas where excessive IR-drop likely occurs without using test vectors and shows that the proposed method can effectively identify areas containing many cells which consume higher power than others.
Abstract: Power-related problems in at-speed scan testing have become more and more serious, since excessive IR-drop caused by excessive power consumption results in overtesting There are two important factors in low-power testing: one is power estimation, the other is power reduction Several estimation methods have been proposed based on the analysis of switching activity characteristics In order to estimate the impact of IR-drop, it is more important to consider the area containing many cells which consume excessive power than to consider the total number of switching activity in a circuit In this paper, we propose a novel method for identifying areas where excessive IR-drop likely occurs without using test vectors Visualized experimental results for IWLS 2005 benchmark circuits demonstrate that the proposed method can effectively identify areas containing many cells which consume higher power than others Such areas identified can be used in low-power test generation so as to achieve effective and efficient results
12 citations
Cites background or methods from "Glitch-Aware Pattern Generation and..."
...Several methods are utilized in order to estimate power consumption or IR-drop [4-13]....
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...On the other hand, it is beneficial to utilize power-related information (such as locations where high power consumption or IR-drop occurs) before test vectors are generated [8]....
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...Low-power test generation reduces the amount of switching activity caused by test vectors [4-12]....
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...These methods [4-13] evaluate whether a given set test vectors cause excessive IR-drop or excessive delay....
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...The methods [8-10] utilize WSA in regional and/or temporal ways by considering location and transition time in a clock cycle....
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TL;DR: A new design-for-testability (DFT) scheme for launch-on-shift (LOS) testing, which ensures that the combinational logic remains undisturbed between the interleaved capture phases, providing computer-aided-design (CAD) tools with extra search space for minimizing launch-to-capture switching activity through test pattern ordering (TPO).
Abstract: Scan-based testing is crucial to ensuring correct functioning of chips. In this scheme, the scan and capture phases are interleaved. It is well known that for large designs, excessive switching activity during the launch-to-capture window leads to high voltage droop on the power grid, ultimately resulting in false delay failures during at-speed test. This article proposes a new design-for-testability (DFT) scheme for launch-on-shift (LOS) testing, which ensures that the combinational logic remains undisturbed between the interleaved capture phases, providing computer-aided-design (CAD) tools with extra search space for minimizing launch-to-capture switching activity through test pattern ordering (TPO). We further propose a new TPO algorithm that keeps track of the don't cares during the ordering process, so that the don't care filling step after the ordering process yields a better reduction in launch-to-capture switching activity compared to any other technique in the literature. The proposed DFT-assisted technique, when applied to circuits in ITC99 benchmark suite, produces an average reduction of 17.68p in peak launch-to-capture switching activity (CSA) compared to the best known lowpower TPO technique. Even for circuits whose test cubes are not rich in don't care bits, the proposed technique produces an average reduction of 15p in peak CSA, while for the circuits with test cubes rich in don't care bits (≥75p), the average reduction is 24p. The proposed technique also reduces the average power dissipation (considering both scan cells and combinational logic) during the scan phase by about 43.5p on an average, compared to the adjacent filling technique.
11 citations
TL;DR: A DFT-based approach for reducing circuit switching activity during scan shift is proposed, which modifies the design at the register transfer level (RTL) and uses the synthesis tools to automatically deal with timing analysis and optimization.
Abstract: Power dissipation in digital circuits during scan-based test is generally much higher than that during functional operation. Unfortunately, this increased test power can create hot spots that may damage the silicon, the bonding wires, and even the package. It can also cause intensive erosion of conductors-severely decreasing the reliability of a device. Finally, excessive test power may also result in extra yield loss. To address these issues, this paper first presents a detailed investigation of a benchmark circuit's switching activity during different modes of operation. Specifically, the average number of transitions in the combinational logic of a benchmark circuit during scan shift is found to be approximately 2.5 times more than the average number of transitions during the circuit's normal functional operation. A DFT-based approach for reducing circuit switching activity during scan shift is proposed. Instead of inserting additional logic at the gate level that may introduce additional delay on critical paths, the proposed method modifies the design at the register transfer level (RTL) and uses the synthesis tools to automatically deal with timing analysis and optimization. Our experiments show that significant power reduction can be achieved with very low overhead.
11 citations
Cites background from "Glitch-Aware Pattern Generation and..."
...…pattern [16], test vector reordering [17], selection of the optimal test sequence [18], and power-aware test pattern generation algorithms [19], [20], etc. Chandra and Kapurt [21] proposed a bounded adjacent X-fill technique where they studied the correlation between the scan-in test stimulus…...
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22 Nov 2015
TL;DR: A novel low power dissipation oriented X-filling method using SAT solvers that conducts simultaneous X- filling for some FFs is proposed that was effective for ISCAS'89 and ITC'99 benchmark circuits compared with justification-probability-based fill.
Abstract: High power dissipation can occur by high launch-induced switching activity when the response to a test pattern is captured by flip-flops (FFs) in at-speed scan testing, resulting in excessive IR drop. IR drop may cause significant capture-induced yield loss in the deep-submicron era. It is known that test modification methods using X-identification and X-filling are effective to reduce power dissipation at the capture cycle. Conventional low power dissipation oriented X-filling methods consecutively select FFs and assign values to reduce the number of transitions on FFs. In this paper, we propose a novel low power dissipation oriented X-filling method using SAT solvers thatconducts simultaneous X-filling for some FFs. We also proposed a selection order of FFs based on a correlation coefficient betweentransitions of FFs and power dissipation. Experimental results show that the proposed method was effective for ISCAS'89 and ITC'99 benchmark circuits compared with justification-probability-based fill.
10 citations
Cites methods from "Glitch-Aware Pattern Generation and..."
...Several methods to reduce capture power on the launch-off capture (LOC) scheme have been proposed[4], [5], [6], [7], [8], [9]....
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...The methods are based on DFT[7], power controller[9], and test data manipulation[4], [5], [6], [8]....
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TL;DR: Based on an effective scan chain configuration, a segment-based X-filling is presented to reduce test power and keep the defect coverage and experimental results show that low testPower and high defect coverage can be achieved.
Abstract: Test power is a serious problem in the scan-based testing. DFT-based techniques and X-filling are two effective ways to reduce both shift power and capture power. However, few of the previous methods pay attention to the defect coverage when reducing the test power. Many of them, especially for X-filling methods, may lead to low defect coverage. In this paper, based on an effective scan chain configuration, we present a segment-based X-filling to reduce test power and keep the defect coverage. The scan chain configuration tries to cluster the scan flip-flops with common successors into one scan chain, in order to distribute the specified bits per pattern over a minimum number of chains. Based on the configuration, all the bits to some scan chains in a vector may be don't care(X). For these scan chains, segment-based X-filling is used to reduce test power and keep the defect coverage. Compared with the ordinary full-scan architecture, experimental results show that low test power and high defect coverage can be achieved.
10 citations
References
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Book•
01 Jan 1990
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
2,758 citations
"Glitch-Aware Pattern Generation and..." refers background in this paper
...When there are several candidate gates in the D-frontier [20], these gates are evaluated based on the size of the timing windows at their outputs and paObjective() selects the candidate gate having the least timing window size....
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IBM1
TL;DR: PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits that uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems and is significantly more efficient than DALG over the general spectrum of combinational Logic circuits.
Abstract: The D-algorithm (DALG) is shown to be ineffective for the class of combinational logic circuits that is used to implement error correction and translation (ECAT) functions. PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits. PODEM uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems. It is shown that PODEM is very efficient for ECAT circuits and is significantly more efficient than DALG over the general spectrum of combinational logic circuits. A distinctive feature of PODEM is its simplicity when compared to the D-algorithm. PODEM is a complete algorithm in that it will generate a test if one exists. Heuristics are used to achieve an efficient implicit search of the space of all possible primary input patterns until either a test is found or the space is exhausted.
1,112 citations
"Glitch-Aware Pattern Generation and..." refers methods in this paper
...Our pattern generation engine is based on the well-known PODEM algorithm [17]....
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TL;DR: This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time.
Abstract: This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG methodology and adopts a very simple flow. It is nonintrusive as it does not require any modifications to the core logic such as the insertion of test points or logic bounding unknown states. The EDT scheme consists of logic embedded on a chip and a new deterministic test-pattern generation technique. The main contributions of the paper are test-stimuli compression schemes that allow us to deliver test data to the on-chip continuous-flow decompressor. In particular, it can be done by repeating certain patterns at the rates, which are adjusted to the requirements of the test cubes. Experimental results show that for industrial circuits with test cubes with very low fill rates, ranging from 3% to 0.2%, these schemes result in compression ratios of 30 to 500 times. A comprehensive analysis of the encoding efficiency of the proposed compression schemes is also provided.
529 citations
"Glitch-Aware Pattern Generation and..." refers methods in this paper
...The compressed stimuli for the test cube is then obtained by solving a system of linear equations corresponding to the inverse function of the decompressor [21]....
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TL;DR: The author reviews low-power testing techniques for VLSI circuits with a discussion of power consumption that gives reasons for and consequences of increased power during test.
Abstract: The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a discussion of power consumption that gives reasons for and consequences of increased power during test. He ends with a discussion of the opportunity to use such techniques in varying situations.
430 citations
01 Sep 2003
TL;DR: This paper discusses the prac- tical issues associated with power consumption during at-speed tests, and delineates in more detail the nature of power-related phenomena encountered in structured speed tests.
Abstract: At-speed test has become a requirement in IC tech- nologies below 180 nm. Unfortunately, test mode switching activity and IR-drop present special chal- lenges to the successful application of structural at- speed tests. In this paper we characterize these prob- lems on commercial ASICs in order to understand how to implement more effective solutions. consumption. Depending on such parameters as gate count, DFT strategies, package type, and other fac- tors, the impact of this problem can range from non- existent to severe. In this paper, we discuss the prac- tical issues associated with power consumption during at-speed tests. We begin by delineating in more detail the nature of power-related phenomena encountered in structured speed tests. We talk about various de- sign features that can be applied to somewhat miti- gate test mode power dissipation. In Section 2, we give a more precise definition of the IR-drop problem which is the focus of this pa- per. We compare IR-drop in slow speed and at-speed structural tests, and also compare it with functional IR-drop. We narrow the focus further to the topic of toggle activity or "switching density" during struc- tured at-speed tests. In Section 3.4 we describe the notion of "quiet" patterns and how they are gener- ated. We follow up with a report of the results we have obtained in experimentation on industrial ASIC designs. Finally we give our suggestions for future work in this area and conclude the paper.
404 citations
"Glitch-Aware Pattern Generation and..." refers background or methods in this paper
...Pattern scrubbing techniques have been previously employed in [1] to overcome such failures....
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...Excessive IR-drop becomes an issue with delay tests, as the launch and capture pulses are applied at-speed [1]....
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...Moreover, highly localized peak test power results in IR-drop related failures [1] and can impact the yield....
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...It has been observed that scan test power is significantly higher than the functional test power [1], [2]....
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