Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test
06 May 2007-pp 167-172
TL;DR: The authors show that glitching activity on nodes must be considered in order to correctly handle constraints on instantaneous peak power and include a power profiler that can analyze a pattern source for violations and a PODEM-based pattern generation engine for generating power-safe patterns.
Abstract: Excessive dynamic voltage drop in the power supply rails during test mode is known to result in false failures and impact yield when testing devices that use low-cost wire-bond packages. Identifying and debugging such test failures is a complex and effort-intensive process, especially when scan compression is involved. From a design cycle-tune view point, it is best to avoid this problem by generating "power-safe" scan patterns. The generation of power-safe patterns must take into consideration the DFT architecture, physical design, tuning and power constraints. In this paper, the authors propose such a framework and show experimental results on some benchmark circuits. The framework can address a non-uniform power grid and region-based power constraints. The authors show that glitching activity on nodes must be considered in order to correctly handle constraints on instantaneous peak power. The framework includes a power profiler that can analyze a pattern source for violations and a PODEM-based pattern generation engine for generating power-safe patterns.
Citations
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01 Sep 2011
TL;DR: A design for testability (DfT) technique to reduce the peak power supply noise (PPSN) during scan chain shifting and the proposed partition technique reduces the maximum flip-flop density that belongs to the same test clock.
Abstract: This paper presents a design for testability (DfT) technique to reduce the peak power supply noise (PPSN) during scan chain shifting. The proposed partition technique reduces the maximum flip-flop density that belongs to the same test clock. The experimental data on large benchmark circuits show that IR drop are reduced by 38.7% on the average compared with the circuit before optimization. Our proposed technique quickly optimizes a half million gate design within 14 minutes while the commercial IR drop simulation tool took over 3 hours.
2 citations
Additional excerpts
...A regional model for ATPG is presented in [20] and a critical path-aware X-filling is shown in [21]....
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19 Mar 2018
TL;DR: This work proposes a virtual wrapper circuitry around the circuit under test (CUT), for test generation purpose, which acts as a shield to obtain power safe vectors and considers analytical power models for power analysis of candidate test vector patterns.
Abstract: Modern circuits with high performance and low power requirements impose strict constraints on manufacturing test generation, particularly on timing test. Delay test is used for performance grading of the circuit. During the application of the test, power consumption has to be less than the functional threshold value, in order to avoid yield loss. This work proposes a new direction to generate power safe test without any changes in DFT (design for testability) structure or existing CAD (computer-aided design) tools. We propose a virtual wrapper circuitry around the circuit under test (CUT), for test generation purpose, which acts as a shield to obtain power safe vectors. The wrapper prohibits the generation of test vector if power consumption exceeds the threshold limits. We consider analytical power models for power analysis of candidate test vector patterns. Experiments performed on benchmark circuits show power safe test generation without coverage loss.
1 citations
Cites background from "Glitch-Aware Pattern Generation and..."
...Another optimization based work which cosiders glitch power is reported in [13] propose modification in PODEM (Path Oriented DEcision making) algorithm to enable safe test generation....
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...The major categories in which research has been developed are: data manipulation of an available test set, innovative ATPG algorithms and better DFT architectures to produced power safe test set [2]-[13]....
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TL;DR: Fundamental techniques of delay testing are introduced to enhance test quality, to avoid over-testing, and to make test design efficient by treating circuits described at register transfer level.
Abstract: Delay testing is one of key processes in production test to ensure high quality and high reliability for logic circuits. Test escape missing defective chips can be reduced by introducing delay testing. On the other hand, we need to concern yield loss caused by delay testing, i.e., over-testing. Many methods and techniques have been developed to solve problems on delay testing. In this paper, we introduce fundamental techniques of delay testing and survey recent problems and solutions. Especially we focus on techniques to enhance test quality, to avoid over-testing, and to make test design efficient by treating circuits described at register transfer level.
1 citations
TL;DR: This paper presents a novel metric called the Transition-TimeRelation-based (TTR) metric which takes transition time relations into consideration in capture-safety checking and greatly improves the accuracy of test vector sign-off and low-capture-power test generation.
Abstract: Test power has become a critical issue, especially for lowpower devices with deeply optimized functional power profiles. Particularly, excessive capture power in at-speed scan testing may cause timing failures that result in test-induced yield loss. This has made capturesafety checking mandatory for test vectors. However, previous capturesafety checking metrics suffer from inadequate accuracy since they ignore the time relations among different transitions caused by a test vector in a circuit. This paper presents a novel metric called the Transition-TimeRelation-based (TTR) metric which takes transition time relations into consideration in capture-safety checking. Detailed analysis done on an industrial circuit has demonstrated the advantages of the TTR metric. Capturesafety checking with the TTR metric greatly improves the accuracy of test vector sign-off and low-capture-power test generation. key words: at-speed testing, ATPG, IR-drop, test power reduction, low power test
1 citations
Cites background from "Glitch-Aware Pattern Generation and..."
...On the other hand, while low-capture-power ATPG [7] is helpful for reducing capture power, its run time is long and the test vector count is large if it must be performed for a large number of faults....
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...Therefore, low-power ATPG must be conducted for only few number of faults undetected by capture-safe vectors previously checked....
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...4© Low-Power ATPG: This dedicated ATPG generates test vectors that achieve both fault detection and low-capture power....
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...3, the low-capture-power ATPG only targets faults undetected by capture-safe vectors identified by capture-safety checking....
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...Since low-power ATPG has constraints for low-power in addition to fault detection, the computation time is always expensive....
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References
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Book•
01 Jan 1990
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
2,758 citations
"Glitch-Aware Pattern Generation and..." refers background in this paper
...When there are several candidate gates in the D-frontier [20], these gates are evaluated based on the size of the timing windows at their outputs and paObjective() selects the candidate gate having the least timing window size....
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IBM1
TL;DR: PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits that uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems and is significantly more efficient than DALG over the general spectrum of combinational Logic circuits.
Abstract: The D-algorithm (DALG) is shown to be ineffective for the class of combinational logic circuits that is used to implement error correction and translation (ECAT) functions. PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits. PODEM uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems. It is shown that PODEM is very efficient for ECAT circuits and is significantly more efficient than DALG over the general spectrum of combinational logic circuits. A distinctive feature of PODEM is its simplicity when compared to the D-algorithm. PODEM is a complete algorithm in that it will generate a test if one exists. Heuristics are used to achieve an efficient implicit search of the space of all possible primary input patterns until either a test is found or the space is exhausted.
1,112 citations
"Glitch-Aware Pattern Generation and..." refers methods in this paper
...Our pattern generation engine is based on the well-known PODEM algorithm [17]....
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TL;DR: This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time.
Abstract: This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG methodology and adopts a very simple flow. It is nonintrusive as it does not require any modifications to the core logic such as the insertion of test points or logic bounding unknown states. The EDT scheme consists of logic embedded on a chip and a new deterministic test-pattern generation technique. The main contributions of the paper are test-stimuli compression schemes that allow us to deliver test data to the on-chip continuous-flow decompressor. In particular, it can be done by repeating certain patterns at the rates, which are adjusted to the requirements of the test cubes. Experimental results show that for industrial circuits with test cubes with very low fill rates, ranging from 3% to 0.2%, these schemes result in compression ratios of 30 to 500 times. A comprehensive analysis of the encoding efficiency of the proposed compression schemes is also provided.
529 citations
"Glitch-Aware Pattern Generation and..." refers methods in this paper
...The compressed stimuli for the test cube is then obtained by solving a system of linear equations corresponding to the inverse function of the decompressor [21]....
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TL;DR: The author reviews low-power testing techniques for VLSI circuits with a discussion of power consumption that gives reasons for and consequences of increased power during test.
Abstract: The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a discussion of power consumption that gives reasons for and consequences of increased power during test. He ends with a discussion of the opportunity to use such techniques in varying situations.
430 citations
01 Sep 2003
TL;DR: This paper discusses the prac- tical issues associated with power consumption during at-speed tests, and delineates in more detail the nature of power-related phenomena encountered in structured speed tests.
Abstract: At-speed test has become a requirement in IC tech- nologies below 180 nm. Unfortunately, test mode switching activity and IR-drop present special chal- lenges to the successful application of structural at- speed tests. In this paper we characterize these prob- lems on commercial ASICs in order to understand how to implement more effective solutions. consumption. Depending on such parameters as gate count, DFT strategies, package type, and other fac- tors, the impact of this problem can range from non- existent to severe. In this paper, we discuss the prac- tical issues associated with power consumption during at-speed tests. We begin by delineating in more detail the nature of power-related phenomena encountered in structured speed tests. We talk about various de- sign features that can be applied to somewhat miti- gate test mode power dissipation. In Section 2, we give a more precise definition of the IR-drop problem which is the focus of this pa- per. We compare IR-drop in slow speed and at-speed structural tests, and also compare it with functional IR-drop. We narrow the focus further to the topic of toggle activity or "switching density" during struc- tured at-speed tests. In Section 3.4 we describe the notion of "quiet" patterns and how they are gener- ated. We follow up with a report of the results we have obtained in experimentation on industrial ASIC designs. Finally we give our suggestions for future work in this area and conclude the paper.
404 citations
"Glitch-Aware Pattern Generation and..." refers background or methods in this paper
...Pattern scrubbing techniques have been previously employed in [1] to overcome such failures....
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...Excessive IR-drop becomes an issue with delay tests, as the launch and capture pulses are applied at-speed [1]....
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...Moreover, highly localized peak test power results in IR-drop related failures [1] and can impact the yield....
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...It has been observed that scan test power is significantly higher than the functional test power [1], [2]....
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