GTL based Internet of Things enable processor specific RAM design on 65nm FPGA
23 Nov 2015-pp 133-136
TL;DR: This work inserted a 128-bit IP address in RAM to make internet of things enable RAM and observed that when the authors use 3.6 GHz operating frequency, there is 90.2% reduction in I/O power when they used GTL instead of GTLP_DCI.
Abstract: In this work, we Energy Efficient Internet of Things (IoTs) Enable RAM is presented. In order to make it energy efficient, used Gunning Transceiver Logic (GTL) IO Standard and Gunning Transceiver Logic Plus (GTLP). We used the 4 different members of GTL and GTLP IO standards family and searched the most energy efficient among them. We observed that when we use 3.6 GHz operating frequency, there is 90.2% reduction in I/O power when we used GTL instead of GTLP_DCI. We have inserted a 128-bit IP address in RAM to make internet of things enable RAM. Finally, we operated our IOTs Enable RAM with different operating frequency of I3, I5, I7, Moto-E and Moto-X.
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01 Jan 2018
TL;DR: The novelty of this work is that it can control the effect of capacitance scaling on junction temperature with the help of addition airflow of 500 Linear Feet per Minute (LFM).
Abstract: A real capacitor will have some power dissipation, whereas an ideal capacitor will not dissipate any power. In this paper, we designed a capacitance scaling-based low-power RAM design. Our work aims to analyze how the memory circuit works using capacitance scaling does and varying temperatures. This design is implemented in Verilog. Usually, for the functioning of a device, the junction temperature is below 125 °C. If we scale down frequency from 10 to 4.5 GHz, 2.3 and 1 GHz then there is 42.96, 59.03, and 70.4% reduction, respectively, in total power at 5 pF output load. With the increase in capacitance, there should be the increase in junction temperature. But the novelty of our work is that we can control the effect of capacitance scaling on junction temperature with the help of addition airflow of 500 Linear Feet per Minute (LFM).
8 citations
01 Jan 2020
TL;DR: This chapter surveys nine different IoT-enabled designs from IoT-based water management cyber-physical system (IoT-WMCPS) to IoTbased random access memory (IiT-RAM), and a platform called Quickscript, used to develop natural language based IoT system.
Abstract: Anything that has an IP address is IoT-enabled. In this chapter, the authors have surveyed nine different IoT-enabled designs from IoT-based water management cyber-physical system (IoT-WMCPS) to IoTbased random access memory (IoT-RAM). They have also surveyed a platform called Quickscript. The Quickscript platform is used to develop natural language based IoT system. The nine different IoT-enabled designs discussed in this chapter are IoT-enabled bicycle called Mo-Bike, IoT-enabled house, IoT-enabled water utility, IoT-enabled mining, IoT-enabled healthcare, IoT-enabled frame buffer, IoT-enabled RAM, IoT-enabled key generator, and IoT-enabled wi-fi encoder. In cyber physical systems for water supply, researchers are able to integrate IPv6 addresses into sensors, actuators, and controllers used in water supply systems. The IPv6 address is integrating into every object available in the city so that researchers may track any object when need occurs. We may locate freely available IoT-enabled bicycles if we need to go anywhere, and we may also trace bicycles in case of theft by criminals. AI and FPGA-Based IoT Architectures, Models, and Platforms for Smart City Application
2 citations
Cites background from "GTL based Internet of Things enable..."
...In this chapter, the authors have surveyed nine different IoT-enabled designs from IoT-based water management cyber-physical system (IoT-WMCPS) to IoTbased random access memory (IoT-RAM)....
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...The nine different IoT-enabled designs discussed in this chapter are IoT-enabled bicycle called Mo-Bike, IoT-enabled house, IoT-enabled water utility, IoT-enabled mining, IoT-enabled healthcare, IoT-enabled frame buffer, IoT-enabled RAM, IoT-enabled key generator, and IoT-enabled wi-fi encoder....
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...…which electronic devices and other equipment will get an IPv6 address to become IoT enable electronic circuits of Frame Buffer (Musavi et al., 2015), RAM (Moudgil et al., 2015; Moudgil et al., 2015) and Encoder (Singh et al., 2015) and Key Generator (Kaur et al., 2014; Kumar, Pandey, & Das, 2013)....
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...This chapter is motivated by the IoT concept and discusses a way through which electronic devices and other equipment will get an IPv6 address to become IoT enable electronic circuits of Frame Buffer (Musavi et al., 2015), RAM (Moudgil et al., 2015; Moudgil et al., 2015) and Encoder (Singh et al., 2015) and Key Generator (Kaur et al., 2014; Kumar, Pandey, & Das, 2013)....
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...Some of these are: IoT facilitates Bicycle, IoT facilitates Coffee Pot, IoT enables Bank, IoT enables Camera, IoT enables Cart, IoT enables House, IoT enables Light Bulb, IoT enables Water Utility, IoT facilitates Car, IoT enables Police Emergency, IoT enables Travel, IoT enables Frame Buffer, IoT enables RAM, IoT facilitates Key Generator, and IoT enables Wi-Fi Encoder....
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TL;DR: In the work the energy efficient and thermal aware single-port RAM has been designed to make it more energy efficient using 28 nm Kintex-7 at ambient temperature of 25 C design tool used is Xilinx 14.2 ISE.
Abstract: In the work the energy efficient and thermal aware single-port RAM has been designed to make it more energy efficient using 28 nm Kintex-7 at ambient temperature of 25 ◦C design tool used is Xilinx 14.2 ISE. Frequency scaling approach has been taken to design energy and power efficient RAM. It is done by scaling frequencies from 50GHz to 200 GHz and calculating the Leakage Power, Quiescent Power as well as the Junction Temperature of Single–Port RAM. Leakage Power has been reduced to the range of 9.411% to 3.52%by Frequency Scaling technique, Quiescent Power Consumption in the range 9.33% to 4.00% and Junction Temperature range from 9.39% to 3.33%, IO Power consumption in range of 45.75% to 15.266% for 50GHz frequency and so on, which makes RAM Design energy efficient and thermal aware.
1 citations
01 Oct 2016
TL;DR: RAM_Read_Control module is designed to control the data read operation to the Random Access Memory (RAM) core that is used for saving the raw data in impedance measurement module of Electrical Impedance Tomography (EIT) system, KHU Mark 2.5.
Abstract: RAM_Read_Control module is designed to control the data read operation to the Random Access Memory (RAM) core. The RAM core is used for saving the raw data in impedance measurement module of Electrical Impedance Tomography (EIT) system, KHU Mark 2.5. The performance of this module is analyzed using XILINX ISE 14.2 design tool on Virtex-5 (xc5vlx20t-ff323) chip. The performance analysis is done for different I/O Standards. HSTL (high speed transceiver logic-I, II, III, IV), LVCMOS15 (low voltage metal oxide semiconductor) and LVTTL (low voltage transistor-transistor logic) I/O standards are used to analyze the performance on Virtex-5 FPGA. This analysis is done at operating frequencies of 400MHz, 500 MHz, 600 MHz and 700 MHz. It is observed that when LVCMOS15 performance results are compared with LVTTL, HSTL_I, II, III, IV at 500MHz, 600MHz, and 700MHz we obtain 65.3%, 65%, 64.5% power reduction respectively. The minimum power reduction is obtained at 700 which are 64.5% when we compared LVCOMS15 with HSTL_IV I/O standard.
TL;DR: A detailed analysis on a low power memory circuit using buffer, extraction and style based RAM design on 28nm Field Programmable Gate Array (FPGA) using Verilog, Xilinx ISE 14.6 simulator with kintex-7 FPGA.
Abstract: In this work, we report a detailed analysis on a low power memory circuit using buffer, extraction and style based RAM design on 28nm Field Programmable Gate Array (FPGA).The designing of this memory circuit is done by Verilog as HDL, Xilinx ISE 14.6 simulator with kintex-7 FPGA. Different RAM styles and RAM extracts are compared on basis of power consumption and reduction. Auto RAM style is the default RAM style and it consumes minimum power as compared to block RAM. The RTL schematic shows I/O ports, nets and primitives. Bufgdll also consumes less power and power reduction is also maximum for bufdll and auto RAM as compared to block RAM, ibufg and RAM extract yes. Auto RAM at 10GHz frequency can be used in designing various applications like in radio astronomy, microwave devices and communications, wireless LAN, most modem radars, communications satellites, satellite television broadcasting.
Cites methods from "GTL based Internet of Things enable..."
...Keywords: Memory, Power Efficient, Low Power, RAM, FPGA...
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...We are designing RAM on 28nm FPGA, while the work have been done on 65nm FPGA [2]....
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...The designing of this memory circuit is done by Verilog as HDL, Xilinx ISE 14.6 simulator with kintex-7 FPGA....
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...For our analysis, Random Access Memory (RAM) circuit of 16-bit with different constraints on FPGA of 28nm is been used so as to make it a most power efficient circuit....
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...Various families of IO standards like SSTL, HSTL, LVCMOS and LVDCI are supported by Kintex-7 FPGA....
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References
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TL;DR: A set of power-efficient logical-to-physical RAM mapping algorithms is described, which converts user-defined memory specifications to on-chip FPGA memory block resources and minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power- efficient choice.
Abstract: Contemporary field-programmable gate array (FPGA) design requires a spectrum of available physical resources. As FPGA logic capacity has grown, locally accessed FPGA embedded memory blocks have increased in importance. When targeting FPGAs, application designers often specify high-level memory functions, which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this paper, a set of power-efficient logical-to-physical RAM mapping algorithms is described, which converts user-defined memory specifications to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-efficient choice. Our automated approach has been validated with both simulation of power dissipation and measurements of power dissipation on FPGA hardware. A comparison of measured power reductions to values determined via simulation confirms the accuracy of our simulation approach. Our power-aware RAM mapping algorithms have been integrated into a commercial FPGA compiler and tested with 34 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 26% and overall core dynamic power can be reduced by 6% with a minimal loss (1%) in design performance. In addition, it is shown that the availability of multiple embedded memory block sizes in an FPGA reduces embedded memory dynamic power by an additional 9.6% by giving more choices to the computer-aided design algorithms
41 citations
01 Dec 2014
TL;DR: Simulation results show that the proposed hierarchical search scheme for RAM-based CAM on FPGA could reduce the power consumption up to 11.0% and 9.7% for block RAM based and distributed RAM based implementation respectively.
Abstract: Content Addressable Memories (CAMs) have been widely used to implement various high speed search functions in network devices such as routers and servers. In these devices, the role of CAM is to classify, drop or forward internet packets (i.e., packet classification). However, CAM suffers from several shortcomings such as high power consumption and low integration density. In addition, CAM is not available in most of modern Field Programmable Gate Array (FPGA), which has broad applications in network infrastructures. Therefore RAM-based CAM emulation has emerged as a promising alternative to CAM not only because RAM is a relatively mature technology but also due to the fact that there are more and larger RAM blocks on modern FPGA. In this paper, we propose a hierarchical search scheme for RAM-based CAM on FPGA. If a match is found in previous blocks, no subsequent search will be triggered and therefore average power consumption is reduced. Comparing with previous works which have not employed this technique, simulation results show that our method could reduce the power consumption up to 11.0% and 9.7% for block RAM based and distributed RAM based implementation respectively.
28 citations
"GTL based Internet of Things enable..." refers background in this paper
...Therefore, we have plenty of IPv6 address, which we can assign for every RAM [2,6-8] and make it internet of things (IoTs) enable RAM....
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01 Dec 2013
TL;DR: In this article, a green image ALU is designed in Xilinx ISE 14.6 using different IO standard of SSTL in 40nm Virtex-6 and Spartan-6 FPGA.
Abstract: In this paper, green Image ALU is designed in Xilinx ISE 14.6 using different IO standard of SSTL in 40nm Virtex-6 and Spartan-6 FPGA. We are comparing different SSTL IO standard to get reduction in IO power. We accomplish energy efficiency with respect to low voltage impedance, by using SSTL technology. In this entire work, we are using different classes of SSTL and observe that when image ALU operates at 1THz device operating frequency with SSTL18_I_DCI I/O Standard using virtex-6 FPGA, there is 45.55% decrease in IO power and 20.50% in Clock power as compared to SSTL18_II IO Standard. Similarly when we operate Image ALU at 1THz using Spartan-6, there is 33.31% reduction in IO power of SSTL18_I with respect to SSTL18_II Standard. There are 16 different arithmetic and logic operations in Image ALU. The Clock power, Logic power and Signal power of Image ALU remains same using Spartan-6 I/O Standard.
22 citations
"GTL based Internet of Things enable..." refers background or methods in this paper
...Earlier SSTL was used in energy efficient design of integrator [3], ROM [4], image ALU [5]....
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...INTRODUCTION Internet of Things (IoTs) [1,5] is a concept in which objects, people or everything around is provided with a unique id....
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...[5] T. Kumar, B. Pandey, T. Das, and M. A. Rahman, "SSTL Based Green Image ALU Design on different FPGA", IEEE International conference on Green Computing, Communication and Conservation of Energy(ICGCE), 12-14 December, 2013....
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01 Nov 2014
TL;DR: This work is operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use, using Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator.
Abstract: Stub Series Terminated Logic (SSTL) is an Input/output standard. It is used to match the impedance of line, port and device of our design under consideration. Therefore, selection of energy efficient SSTL I/O standard among available different class of SSTL logic family in FPGA, plays a vital role to achieve energy efficiency in design under test (DUT). Here, DUT is ROM. ROM is an integral part of processor. Therefore, energy efficient design of RAM is a building block of energy efficient processor. We are using Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator. We are operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use. When there is no demand of peak performance, then we can save 74.5% clock power, 75% signal power, and 30.83% I/O power by operating our device with 1GHz frequency in place of 4GHz. There is no change in clock power and signal power but SSTL2_H_DCI having 80.24% 83.38% 62.92% and 76.52% and 83.03% more I/O power consumption with respect to SSTL2_I, SST18_I, SSTL2_I_DCI, SSTL2_II, and SSTL15 respectively at 3.3GHz.
14 citations
22 Apr 2014
TL;DR: In this paper, green Integrator is implemented using various IO standard of SSTL in 28nm Kintex-7 FPGA to get minimum IO power and dynamic clock power variations it's almost same in every frequency i.e. 15%.
Abstract: In this paper, we are implementing green Integrator. Digital integrator is an analog to digital converter. Which is designed in Xilinx ISE14.6 using various IO standard of SSTL in 28nm Kintex-7 FPGA. We are comparing different IO standard of SSTL to get minimum IO power. Via SSTL technology, we achieve green computing with respect to low voltage impedance. We are using different classes of SSTL in this entire paper and analyzed that when integrator device operating frequency is 1THz then there is 76.65% reduction in IO power of SSTL135_DCI as compare to SSTL135_R I/O Standard on Kintex-7 FPGA. Likewise at 2GHz, our integrator IO power reduction is 70.14% of SSTL12 with respect to SSTL12_DCI of IO standard using kintex-7 FPGA. When we see the dynamic clock power variations it's almost same in every frequency i.e. 15%. Similarly when we operate parallel integrator at 200 GHz via kintex-7, there is 28.12% decrease in signal power of SSTL135_R with respect to SSTL135_DCI Standard. The Leakage power of integrator is decrease 16.21% of SSTL135_DCI as compared to SSTL135_R at 1 THz device operating frequency.
7 citations