Journal ArticleDOI
Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs
Debasri Saha,Susmita Sur-Kolay +1 more
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TLDR
This paper proposes an evolutionary computation approach to handle the problem of placement followed by the assignment of through-silicon vias of 3-D ICs in a novel way so that, on exploration of a variety of nondominated solutions, the search process converges to a near-optimum solution in reasonable time.Abstract:
The advent of 3-D IC technology facilitates the fabrication of large electronic circuits on small-area chips ensuring high performance. For a 3-D IC, the problem of placement followed by the assignment of through-silicon vias (TSVs) involves optimizing various design objectives such as intertier wirelength, power density, congestion, and separation between the TSVs. Each of the existing techniques for the placement of TSVs deals only with a subset of these objectives. In this paper, we propose an evolutionary computation approach $MO\_{}TSV$ to handle this multiobjective optimization problem. The operators, parameters, and constituents of the framework of genetic algorithm (GA)-based multiobjective optimization have been designed in a novel way so that, on exploration of a variety of nondominated solutions, the search process converges to a near-optimum solution in reasonable time. Experimental results on ISCAS’85, ISCAS’89, ITC’99, and IBM (ISPD’98) benchmarks yield quality solutions in terms of all the parameters as well as convergence times, which are encouraging.read more
Citations
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Journal ArticleDOI
An evolutionary approach to implement logic circuits on three dimensional FPGAs
H. Rahimi,Hadi Jahanirad +1 more
TL;DR: A complete Computer Aided Design (CAD) flow to implement an arbitrary logic circuit on 3D FPGA is proposed and simulation results show more than 60%, 65%, and 23% reduction in TSV count, heat transfer performance, and area respectively, along with 4% increase in critical path delay.
Journal ArticleDOI
Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs
TL;DR: This work proposes a heuristic procedure to determine the placement of wrapper elements in several layers of 3D SOC for a number of wrapper chains and interconnect them using available number of TSVs such that the length of the longest wrapper length (LWL) is minimized.
Journal ArticleDOI
The Fellini Museum of Rimini in Italy and the Genetic Algorithms-Based Method to Optimize the Design of an Integrated System Network and Installations
TL;DR: The Fellini Museum of Rimini is an exhibition hall dedicated to the Rimini film director Federico Fellini, included by the Ministry of Culture of Italy among the great national cultural projects as mentioned in this paper .
Book ChapterDOI
Fundamentals of Heat Dissipation in 3D IC Packaging and Thermal-Aware Design
TL;DR: An overview of the available cooling options for 3D ICs and their performance evaluation are presented in this paper, along with an overview of interlayer cooling with microchannels and introducing fins in the coolant flow paths.
Proceedings ArticleDOI
Particle Swarm Optimization and Genetic Algorithms for PID Controller Tuning
TL;DR: In this article , the tuning of an inverted pendulum's proportional-integral-derivative (PID) parameters using heuristic approaches is compared. But the tuning process is subsequently turned into an optimization issue and a mix of particle swarm optimization and genetic algorithms are used to overcome this issue.
References
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Journal ArticleDOI
TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model
TL;DR: This paper proposes a new 3-D cell placement algorithm that can additionally consider the sizes of TSVs and the physical positions for TSV insertion during placement, and can achieve the best routed wirelength, TSV counts, and total silicon area, in shortest running time.
Proceedings ArticleDOI
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
TL;DR: A state-of-the-art recursive bisection placer is tuned to betterhandle regular netlists that offer a convenient way to represent memories, datapaths and random-logic IP blocks and better whitespace distribution improve results on recent mixed-size placement benchmarks.
Journal ArticleDOI
An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness
Guojie Luo,Yiyu Shi,Jason Cong +2 more
TL;DR: The experimental results show that this analytical approach is effective for achieving tradeoffs between the wirelength and the through-silicon-via (TSV) number, and suggest that considering the thermal effects of TSVs is necessary and effective during the placement stage.
Journal ArticleDOI
Planning Massive Interconnects in 3-D Chips
TL;DR: A novel 3-D-floorplanning methodology is proposed which accounts for different types of interconnects in a unified manner, and one key idea is to align cores/blocks simultaneously within and across dies, thus increasing the likelihood of successfully implementing complex and massive interConnects.
Journal ArticleDOI
CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits
TL;DR: Experimental results have shown that the proposed congestion-driven 3D supercell placement and flow-based 3D-via-assignment tools have yielded satisfactory placement with small-area, low-congestion, short-wire-length, few, and uniformly distributed 3D vias.