Journal ArticleDOI
Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs
Debasri Saha,Susmita Sur-Kolay +1 more
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TLDR
This paper proposes an evolutionary computation approach to handle the problem of placement followed by the assignment of through-silicon vias of 3-D ICs in a novel way so that, on exploration of a variety of nondominated solutions, the search process converges to a near-optimum solution in reasonable time.Abstract:
The advent of 3-D IC technology facilitates the fabrication of large electronic circuits on small-area chips ensuring high performance. For a 3-D IC, the problem of placement followed by the assignment of through-silicon vias (TSVs) involves optimizing various design objectives such as intertier wirelength, power density, congestion, and separation between the TSVs. Each of the existing techniques for the placement of TSVs deals only with a subset of these objectives. In this paper, we propose an evolutionary computation approach $MO\_{}TSV$ to handle this multiobjective optimization problem. The operators, parameters, and constituents of the framework of genetic algorithm (GA)-based multiobjective optimization have been designed in a novel way so that, on exploration of a variety of nondominated solutions, the search process converges to a near-optimum solution in reasonable time. Experimental results on ISCAS’85, ISCAS’89, ITC’99, and IBM (ISPD’98) benchmarks yield quality solutions in terms of all the parameters as well as convergence times, which are encouraging.read more
Citations
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Journal ArticleDOI
An evolutionary approach to implement logic circuits on three dimensional FPGAs
H. Rahimi,Hadi Jahanirad +1 more
TL;DR: A complete Computer Aided Design (CAD) flow to implement an arbitrary logic circuit on 3D FPGA is proposed and simulation results show more than 60%, 65%, and 23% reduction in TSV count, heat transfer performance, and area respectively, along with 4% increase in critical path delay.
Journal ArticleDOI
Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs
TL;DR: This work proposes a heuristic procedure to determine the placement of wrapper elements in several layers of 3D SOC for a number of wrapper chains and interconnect them using available number of TSVs such that the length of the longest wrapper length (LWL) is minimized.
Journal ArticleDOI
The Fellini Museum of Rimini in Italy and the Genetic Algorithms-Based Method to Optimize the Design of an Integrated System Network and Installations
TL;DR: The Fellini Museum of Rimini is an exhibition hall dedicated to the Rimini film director Federico Fellini, included by the Ministry of Culture of Italy among the great national cultural projects as mentioned in this paper .
Book ChapterDOI
Fundamentals of Heat Dissipation in 3D IC Packaging and Thermal-Aware Design
TL;DR: An overview of the available cooling options for 3D ICs and their performance evaluation are presented in this paper, along with an overview of interlayer cooling with microchannels and introducing fins in the coolant flow paths.
Proceedings ArticleDOI
Particle Swarm Optimization and Genetic Algorithms for PID Controller Tuning
TL;DR: In this article , the tuning of an inverted pendulum's proportional-integral-derivative (PID) parameters using heuristic approaches is compared. But the tuning process is subsequently turned into an optimization issue and a mix of particle swarm optimization and genetic algorithms are used to overcome this issue.
References
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Journal ArticleDOI
3D thermal-aware floorplanner using a MOEA approximation
TL;DR: This work proposes a novel 3D thermal-aware floorplanner for many-core single-chip architectures and shows promising improvements of the mean and peak temperature, as well as the thermal gradient, with a reduced overhead in the wire length of the system.
Proceedings ArticleDOI
Multiobjective optimization of deadspace, a critical resource for 3D-IC integration
TL;DR: A lightweight multiobjective deadspace-optimization methodology that simultaneously optimizes interconnect, IR-drop, clock-tree size and maximal temperature is proposed.
Journal ArticleDOI
TSV- and delay-aware 3D-IC floorplanning
TL;DR: A novel floorplanning algorithm for 3D ICs with through-silicon vias (TSVs) that directly optimizes delay due to wires and TSVs is proposed that results in more effective delay minimization.
Book ChapterDOI
Three-Dimensional Integration: A More Than Moore Technology
TL;DR: Three-dimensional integrated circuits, which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density, but before these advantages can be realized, key technology and CAD challenges of 3D-ICs must be addressed.
Proceedings ArticleDOI
Fast global interconnnect driven 3D floorplanning
TL;DR: This work presents a new global interconnect driven 3D floorplanner which simultaneously optimizes global inter connect routes, performs TSV placement, and accounts for fixed-outline floorplanning.