Guided multilevel approximation of less significant bits for power reduction
01 May 2016-pp 1-6
TL;DR: A generic technique, guided multilevel approximation, by which most of the basic arithmetic circuits of a media processing application can be built, and power saving ranging from 30% to 75% is obtained with minimum loss of accuracy.
Abstract: Approximate circuit design has gained significance in recent years targeting applications like media processing where 100% accuracy is not mandatory. Though different approximate adders and multipliers are described in the literature, there is no common approach yet by which many arithmetic circuits can be designed. In this paper we propose a generic technique, guided multilevel approximation, by which most of the basic arithmetic circuits of a media processing application can be built. Basic circuits such as adders, multipliers, filters and multiply-accumulate units are designed using the straight-forward generic technique and power saving ranging from 30% to 75% is obtained with minimum loss of accuracy.
References
More filters
27 May 2013
TL;DR: This paper reviews recent progress in the area, including design of approximate arithmetic blocks, pertinent error and quality measures, and algorithm-level techniques for approximate computing.
Abstract: Approximate computing has recently emerged as a promising approach to energy-efficient design of digital systems. Approximate computing relies on the ability of many systems and applications to tolerate some loss of quality or optimality in the computed result. By relaxing the need for fully precise or completely deterministic operations, approximate computing techniques allow substantially improved energy efficiency. This paper reviews recent progress in the area, including design of approximate arithmetic blocks, pertinent error and quality measures, and algorithm-level techniques for approximate computing.
921 citations
"Guided multilevel approximation of ..." refers methods in this paper
...Voltage scaling and architectural approximation are two main approaches used to reduce power in circuits by making them approximate [1], [2]....
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TL;DR: This paper proposes logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy, and demonstrates the utility of these approximate adders in two digital signal processing architectures with specific quality constraints.
Abstract: Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. We design architectures for video and image compression algorithms using the proposed approximate arithmetic units and evaluate them to demonstrate the efficacy of our approach. We also derive simple mathematical models for error and power consumption of these approximate adders. Furthermore, we demonstrate the utility of these approximate adders in two digital signal processing architectures (discrete cosine transform and finite impulse response filter) with specific quality constraints. Simulation results indicate up to 69% power savings using the proposed approximate adders, when compared to existing implementations using accurate adders.
637 citations
"Guided multilevel approximation of ..." refers methods in this paper
...In architectural approximation, many techniques like bitwidth truncation, segmentation, truth table based approximation, transistor-level approximation have been proposed [2], [5]....
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TL;DR: It is shown that these proposed Bio-inspired Imprecise Computational blocks (BICs) can be exploited to efficiently implement a three-layer face recognition neural network and the hardware defuzzification block of a fuzzy processor.
Abstract: The conventional digital hardware computational blocks with different structures are designed to compute the precise results of the assigned calculations. The main contribution of our proposed Bio-inspired Imprecise Computational blocks (BICs) is that they are designed to provide an applicable estimation of the result instead of its precise value at a lower cost. These novel structures are more efficient in terms of area, speed, and power consumption with respect to their precise rivals. Complete descriptions of sample BIC adder and multiplier structures as well as their error behaviors and synthesis results are introduced in this paper. It is then shown that these BIC structures can be exploited to efficiently implement a three-layer face recognition neural network and the hardware defuzzification block of a fuzzy processor.
458 citations
"Guided multilevel approximation of ..." refers background in this paper
...In [6], lower-part OR adder is designed where LSB part of the sum is approximated as OR of the corresponding inputs and carry input from LSB part is ignored....
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02 Jan 2011
TL;DR: A novel multiplier architecture with tunable error characteristics, that leverages a modified inaccurate 2x2 building block, that can achieve 2X - 8X better Signal-Noise-Ratio (SNR) for the same power savings when compared to recent voltage over-scaling based power-error tradeoff methods is proposed.
Abstract: We propose a novel multiplier architecture with tunable error characteristics, that leverages a modified inaccurate 2x2 building block. Our inaccurate multipliers achieve an average power saving of 31.78% ? 45.4% over corresponding accurate multiplier designs, for an average error of 1.39%?3.32%. Using image filtering and JPEG compression as sample applications we show that our architecture can achieve 2X - 8X better Signal-Noise-Ratio (SNR) for the same power savings when compared to recent voltage over-scaling based power-error tradeoff methods. We project the multiplier power savings to bigger designs highlighting the fact that the benefits are strongly design dependent. We compare this circuit-centric approach to power quality tradeoffs with a pure software adaptation approach for a JPEG example. We also enhance the design to allow for correct operation of the multiplier using a residual adder, for non error resilient applications.
411 citations
"Guided multilevel approximation of ..." refers methods in this paper
...In [10], an approximate 2bit multiplier is designed and is used to construct bigger multipliers....
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...GAM are compared with that of different approximate multipliers in the literature like Error Tolerant Multiplier [9] (ETM) and Multiplier using 2× 2 approximate multiplier [10] (Mult) and accurate multiplier (AM) as shown in Fig....
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03 Jun 2012
TL;DR: This paper proposes an accuracy-configurable approximate adder for which the accuracy of results is configurable during runtime, and can be used in accuracy- configurable applications, and improves the achievable tradeoff between performance/power and quality.
Abstract: Approximation can increase performance or reduce power consumption with a simplified or inaccurate circuit in application contexts where strict requirements are relaxed. For applications related to human senses, approximate arithmetic can be used to generate sufficient results rather than absolutely accurate results. Approximate design exploits a tradeoff of accuracy in computation versus performance and power. However, required accuracy varies according to applications, and 100% accurate results are still required in some situations. In this paper, we propose an accuracy-configurable approximate (ACA) adder for which the accuracy of results is configurable during runtime. Because of its configurability, the ACA adder can adaptively operate in both approximate (inaccurate) mode and accurate mode. The proposed adder can achieve significant throughput improvement and total power reduction over conventional adder designs. It can be used in accuracy-configurable applications, and improves the achievable tradeoff between performance/power and quality. The ACA adder achieves approximately 30% power reduction versus the conventional pipelined adder at the relaxed accuracy requirement.
385 citations
"Guided multilevel approximation of ..." refers background or methods in this paper
...In [4], Accuracy Configurable Adder (ACA) is designed with error correcting capability....
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...To measure the accuracy and quality of approximate circuits, metrics like normalized mean error distance, mean relative error distance, error rate, error significance, peak signal to noise ratio are used [3], [4]....
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