Hardware acceleration in computer networks

TLDR: This tutorial deals with parsing of packet headers, longest prefix matching (IP look-up), packet classification and regular expression matching, which have to be accelerated to achieve 100 Gb throughput.

Abstract: Summary form only given. Network traffic processing speed is crucial in most of network devices, because any packet drop can lead to lower quality of network services, affect precise monitoring or disallow detection of security threats. General purpose processors are not able to process all data on high-speed network links. For 100 Gb lines, packet can arrive every 5 ns. Therefore network devices use hardware acceleration to speed up time-critical operations. In this tutorial, we will introduce these time-critical operations together with hardware architectures, which are able to achieve 10, 40 or even 100 Gbps throughput. In particular, the tutorial deals with parsing of packet headers, longest prefix matching (IP look-up), packet classification and regular expression matching. All these operations are widely used in network security and monitoring devices and have to be accelerated to achieve 100 Gb throughput. We will present that deep pipelines, perfect hashing and efficient utilization of on-chip memory can help to achieve high throughput or decrease hardware resources. The end of the presentation will be devoted to the rapid development of hardware accelerated network applications for 100 Gbps networks. In summary, tutorial participants will become familiar with the state of the art algorithms and hardware architectures for high speed packet processing. They will learn how to utilize these architectures and accelerate network applications.