Hardware Design of a Turbo Product Code Decoder
01 Jan 2021-pp 249-255
TL;DR: In this paper, the authors have discussed the hardware design of an error control decoder, namely turbo product code decoder using both MATLAB and Verilog, and its performance has been analyzed.
Abstract: In a communication channel, message transfer happens through a noisy medium which can introduce errors in the transmitted message. It is required to maintain an acceptable bit error rate for a reliable transmission. This can be handled by an efficient error control coding scheme. This paper discusses the hardware design of an error control decoder, namely turbo product code decoder. The iterative Chase-Pyndiah decoding algorithm has been used in the turbo decoder design. The decoder has been designed using both MATLAB and Verilog, and its performance has been analysed. To study the robustness of the decoder in dealing with different data types, performance analysis is done with both the received data and the encrypted version of the same. Advanced Encryption Standard (AES) has been used for the encryption process, and it is shown that there is only a negligible difference in the performance for both the data sets.
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01 Jan 2023
TL;DR: In this article , the design of a high-speed and low-power advanced encryption standard (AES) architecture to be used as a hardware accelerator in various cryptographic systems is explored.
Abstract: Data security is becoming a major concern in recent years due to the proliferation of interconnected devices. With the number of devices connected to the Internet of things (IoT) growing at a very rapid pace, design of speed and power efficient crypto systems is very essential. This paper explores the design of a high-speed and low-power advanced encryption standard (AES) architecture to be used as a hardware accelerator in various cryptographic systems. The use of Rijndael S-Box for byte substitution, merging of ShiftRows operation with the State Register updation, implementation of MixColumns transformation through substructure sharing, and clock gating methods are investigated in this work for obtaining a high-speed device with low-power consumption. The proposed design is designed using Verilog and co-simulated in MATLAB and implemented as an ASIC using 90 nm GPDK technology. It is seen that the proposed design has 83% increase in speed, 39% decrease in area, and 82% reduction in power dissipation as compared to a standard AES design implementation.
TL;DR: In this paper , the design and implementation of a low power and area efficient AES architecture has been discussed, which is achieved by avoiding the use of registers and using ROM during the sorting operation of AddRound keys and by merging of shift row operation and byte substitution.
Abstract: The tremendous increase in information transmission and data storage has lead to a high demand for secure information storage and transfer. Various security services for a wide range of applications use Advanced Encryption Standard (AES) as the default algorithm for encryption. With an ubiquitous access to information through mobile and handheld devices, the need for providing security with minimum area and power consumption is very essential. This paper deals with the design and implementation of a low power and area efficient AES architecture. This is achieved by avoiding the use of registers and using ROM during the sorting operation of AddRound keys and by merging of shift row operation and byte substitution. Further reduction in area and power is achieved by using a rotational shift instead of the standard cyclic shifting during the ShiftRow operation. The results from the study indicate that implementation of the proposed design on a Virtex-7 FPGA utilizes 62% less slice registers and 47% less slice LUTs as compared to the standard AES design. Moreover, calculation of power and area in 90 nm GPDK technology results in 30% reduced area and 75% less power.
14 Oct 2022
TL;DR: In this paper , the design and implementation of a low power and area efficient AES architecture has been discussed, which is achieved by avoiding the use of registers and using ROM during the sorting operation of AddRound keys and by merging of shift row operation and byte substitution.
Abstract: The tremendous increase in information transmission and data storage has lead to a high demand for secure information storage and transfer. Various security services for a wide range of applications use Advanced Encryption Standard (AES) as the default algorithm for encryption. With an ubiquitous access to information through mobile and handheld devices, the need for providing security with minimum area and power consumption is very essential. This paper deals with the design and implementation of a low power and area efficient AES architecture. This is achieved by avoiding the use of registers and using ROM during the sorting operation of AddRound keys and by merging of shift row operation and byte substitution. Further reduction in area and power is achieved by using a rotational shift instead of the standard cyclic shifting during the ShiftRow operation. The results from the study indicate that implementation of the proposed design on a Virtex-7 FPGA utilizes 62% less slice registers and 47% less slice LUTs as compared to the standard AES design. Moreover, calculation of power and area in 90 nm GPDK technology results in 30% reduced area and 75% less power.
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TL;DR: An iterative decoding algorithm for any product code built using linear block codes based on soft-input/soft-output decoders for decoding the component codes so that near-optimum performance is obtained at each iteration.
Abstract: This paper describes an iterative decoding algorithm for any product code built using linear block codes. It is based on soft-input/soft-output decoders for decoding the component codes so that near-optimum performance is obtained at each iteration. This soft-input/soft-output decoder is a Chase decoder which delivers soft outputs instead of binary decisions. The soft output of the decoder is an estimation of the log-likelihood ratio (LLR) of the binary decisions given by the Chase decoder. The theoretical justifications of this algorithm are developed and the method used for computing the soft output is fully described. The iterative decoding of product codes is also known as the block turbo code (BTC) because the concept is quite similar to turbo codes based on iterative decoding of concatenated recursive convolutional codes. The performance of different Bose-Chaudhuri-Hocquenghem (BCH)-BTCs are given for the Gaussian and the Rayleigh channel. Performance on the Gaussian channel indicates that data transmission at 0.8 dB of Shannon's limit or more than 98% (R/C>0.98) of channel capacity can be achieved with high-code-rate BTC using only four iterations. For the Rayleigh channel, the slope of the bit-error rate (BER) curve is as steep as for the Gaussian channel without using channel state information.
970 citations
TL;DR: The algorithm proposed here presents a major advantage over existing decoding algorithms for BTCs by providing ample flexibility in terms of performance-complexity tradeoff, which makes the algorithm well suited for wireless multimedia applications.
Abstract: An efficient soft-input soft-output iterative decoding algorithm for block turbo codes (BTCs) is proposed. The proposed algorithm utilizes Kaneko's (1994) decoding algorithm for soft-input hard-output decoding. These hard outputs are converted to soft-decisions using reliability calculations. Three different schemes for reliability calculations incorporating different levels of approximation are suggested. The algorithm proposed here presents a major advantage over existing decoding algorithms for BTCs by providing ample flexibility in terms of performance-complexity tradeoff. This makes the algorithm well suited for wireless multimedia applications. The algorithm can be used for optimal as well as suboptimal decoding. The suboptimal versions of the algorithm can be developed by changing a single parameter (the number of error patterns to be generated). For any performance, the computational complexity of the proposed algorithm is less than the computational complexity of similar existing algorithms. Simulation results for the decoding algorithm for different two-dimensional BTCs over an additive white Gaussian noise channel are shown. A performance comparison of the proposed algorithm with similar existing algorithms is also presented.
60 citations
TL;DR: A new encoding scheme is presented for extended turbo product codes for which the operations of looking up and fetching error patterns are no longer necessary, and thus the lookup table can be omitted.
Abstract: In this letter, we propose a low complexity algorithm for extended turbo product codes by considering both the encoding and decoding aspects For the encoding part, a new encoding scheme is presented for which the operations of looking up and fetching error patterns are no longer necessary, and thus the lookup table can be omitted For the decoder, a new algorithm is proposed to extract the extrinsic information and reduce the redundancy This new algorithm can reduce decoding complexity greatly and enhance the performance of the decoder Simulation results are presented to show the effectiveness of the proposed scheme
19 citations
01 Sep 2017
TL;DR: The model describes decoder functioning taking into account limitations of hardware platform and proposes re-use of components in the decoding process and the method provides set of steps for decoder implementation.
Abstract: Model of Turbo-Product Codes decoder architecture and method for construction of Turbo-Product Codes decoder are proposed in the paper. The model describes decoder functioning taking into account limitations of hardware platform and proposes re-use of components in the decoding process. The method provides set of steps for decoder implementation. Field-Programmable Gate Arrays circuits are selected as hardware platform. Implemented decoder demonstrates high throughput and can decode codes that consist of Hamming codes with different codeword length that can be configured “on-the-fly”.
12 citations
05 May 2010
TL;DR: Simulation results demonstrate that the decoding complexity can be effectively reduced and the bit-error rate can be improved slightly, compared with a conventional TPC decoder in both serial and parallel decoding manners.
Abstract: We presents a hybrid decoder, which adopts a soft-input soft-output or a hard-input soft-output scheme to decode a row/column vector in each iteration for iterative decoding a turbo product code, based on the syndrome of the row/column vector. Simulation results demonstrate that the decoding complexity can be effectively reduced and the bit-error rate can be improved slightly, compared with a conventional TPC decoder in both serial and parallel decoding manners.
11 citations