Harmonic Analysis and Controller Design of 15 kV SiC IGBT-Based Medium-Voltage Grid-Connected Three-Phase Three-Level NPC Converter
TL;DR: In this article, the harmonic performance and current distortion of the grid-connected, three-level neutral point clamped converter using 15 kV silicon carbide Insulated Gate Bipolar Transistor (IGBTs) are investigated.
Abstract: Cascaded converters are generally used for medium-voltage (MV) grid-connected applications due to the limitation in the voltage rating of available silicon (Si) power devices. These converters find application in active power filters, STATCOM or as the active front end converters for solid state transformers at the distribution voltage levels. The high voltage wide bandgap semiconductor devices have enabled the grid connected operation of noncascaded converters. This results in high power density, less number of switching devices, and high efficiency for three-phase MV grid interface. This also results in control simplicity without the need for complex dc bus balancing algorithms otherwise needed for cascaded converters. However, such noncascaded, grid-connected converters introduce challenges in maintaining power quality at low currents. This paper investigates the harmonic performance and current distortion of the grid-connected, three-level neutral point clamped converter using 15 kV silicon carbide Insulated Gate Bipolar Transistor (IGBTs). A suitable control scheme for stable harmonic compensation is proposed. The challenges and control performance are explained through frequency domain analysis, simulations, and experimental validation on a developed prototype of the three-phase converter up to 4.16 kV, three-phase MV grid-connected operation.
Citations
More filters
TL;DR: This review comprehensively reviews the SST topologies suitable for different voltage levels and with varied stages, their control operation, and different trends in applications and provides recommendations for the improvement of future SST configuration and development.
Abstract: Solid-state transformer (SST) is an emerging technology integrating with a transformer power electronics converters and control circuitry. This paper comprehensively reviews the SST topologies suitable for different voltage levels and with varied stages, their control operation, and different trends in applications. The paper discusses various SST configurations with their design and characteristics to convert the input to output under unipolar and bipolar operation. A comparison between the topologies, control operation and applications are included. Different control models and schemes are explained. Potential benefits of SST in many applications in terms of controllability and the synergy of AC and DC systems are highlighted to appreciate the importance of SST technologies. This review highlights many factors including existing issues and challenges and provides recommendations for the improvement of future SST configuration and development.
175 citations
Cites background from "Harmonic Analysis and Controller De..."
...However, it brought to the challenges in maintaining the power quality at low current/low load conditions [61], [62]....
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TL;DR: A novel virtual space vector modulation, named as RCMV_VSVPWM, is proposed in this paper to reduce CMV and eliminate NP voltage oscillation for NPC TLI, and the highlight of the method is zero average NP current in one control cycle and lower CMV.
Abstract: This paper briefly reviews the common-mode voltage (CMV) and neutral point (NP) voltage for neutral point clamped three-level inverter (NPC TLI). Then, the space vector pulsewidth modulation (SVPWM) and traditional virtual SVPWM (VSVPWM) are discussed in terms of these two issues, revealing the drawbacks in reducing CMV or eliminating NP voltage oscillation. A novel virtual space vector modulation, named as RCMV_VSVPWM, is proposed in this paper to reduce CMV and eliminate NP voltage oscillation for NPC TLI. By selecting vectors with lower CMVs, a set of novel virtual voltage vectors are generated. The highlight of the method is zero average NP current in one control cycle and lower CMV. Furthermore, the active NP voltage control suitable for RCMV_VSVPWM is presented and evaluated. The corresponding experimental results are given, which are well-consistent with theoretical analysis.
82 citations
TL;DR: This paper investigates the use of the multilevel modular converter (MMC) for harmonics mitigation due to its high bandwidth compared with conventional converters and proves the capability of the MMC to mitigate harmonics up to the thirteenth order, while maintaining a low effective switching frequency and thus, low switching losses.
Abstract: Due to the increase of power electronic-based loads, the maintenance of high power quality poses a challenge in modern power systems. To limit the total harmonic distortion in the line voltage and currents at the point of the common coupling (PCC), active power filters are commonly employed. This paper investigates the use of the multilevel modular converter (MMC) for harmonics mitigation due to its high bandwidth compared with conventional converters. A selective harmonics detection method and a harmonics controller are implemented, while the output current controller of the MMC is tuned to selectively inject the necessary harmonic currents. Unlike previous studies, focus is laid on the experimental verification of the active filtering capability of the MMC. For this reason an MMC-based double-star STATCOM is developed and tested for two representative case studies, i.e., for grid currents and PCC voltage harmonics. The results verify the capability of the MMC to mitigate harmonics up to the thirteenth order, while maintaining a low effective switching frequency and thus, low switching losses.
52 citations
Cites background from "Harmonic Analysis and Controller De..."
...Several open-loop control schemes using grid voltage feed-forward have been proposed to compensate the grid harmonic voltage [10]–[13], but they are not sufficient to suppress line current harmonics due to dead time effect [14]....
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...Both implementations are equivalent in terms of computational burden [10] and thus, high bandwidth is necessary for the current control loops in order to have satisfactory results in the elimination of steady-state errors [14]....
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...At medium voltage and low current, there is little margin for error and thus, feedforward compensation schemes are not preferred, whereas feedback-based approaches are recommended [14]....
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TL;DR: A state-of-the-art review for SST proposed topologies, controllers, and applications is introduced and strengths, weaknesses, opportunities, and threats (SWOT) analysis along with a brief review of market drivers for prospective commercialisation are elaborated.
Abstract: With the global trend to produce clean electrical energy, the penetration of renewable energy sources in existing electricity infrastructure is expected to increase significantly within the next few years. The solid state transformer (SST) is expected to play an essential role in future smart grid topologies. Unlike traditional magnetic transformer, SST is flexible enough to be of modular construction, enabling bi-directional power flow and can be employed for AC and DC grids. Moreover, SSTs can control the voltage level and modulate both active and reactive power at the point of common coupling without the need to external flexible AC transmission system device as per the current practice in conventional electricity grids. The rapid advancement in power semiconductors switching speed and power handling capacity will soon allow for the commercialisation of grid-rated SSTs. This paper is aimed at introducing a state-of-the-art review for SST proposed topologies, controllers, and applications. Additionally, strengths, weaknesses, opportunities, and threats (SWOT) analysis along with a brief review of market drivers for prospective commercialisation are elaborated.
38 citations
TL;DR: A power management strategy to address the unpredictability of the solar irradiance fluctuations with two main operation modes: first, the load-feeding mode to minimize the grid power consumption by maximizing the local load consumption from both the PV and the EBU; second, the grid- feeding mode to smooth out the PV output fluctuation and to control the ramp rate to a desired value when supplying the grid.
Abstract: The unpredictability of the solar irradiance fluctuations can result in both photovoltaic (PV) power output fluctuations and high ramp rates. This can lead to significant voltage fluctuations with high ramp rates at the point of common coupling. Traditionally, the energy buffer units (EBUs) are used to smooth out the power fluctuations using the moving average method or the PV power gradient control. However, these methods can only smooth out the power at the output of grid inverter without considering the local load. This paper proposes a power management strategy to address this issue with two main operation modes: first, the load-feeding mode to minimize the grid power consumption by maximizing the local load consumption from both the PV and the EBU; second, the grid-feeding mode to smooth out the PV output fluctuation and to control the ramp rate to a desired value when supplying the grid. Furthermore, the EBU can be fully charged during the off-peak period or at night by the grid to take advantage of the time-of-use electricity price. The proposed control strategy is first simulated using MATLAB/Simulink and then a laboratory prototype platform is built and tested to verify the feasibility and the effectiveness of the proposed power management strategy with ramp-rate control.
38 citations
Cites background from "Harmonic Analysis and Controller De..."
...is becoming an attractive topology for interfacing renewable energy sources to the grid [23]–[25]....
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References
More filters
TL;DR: The novel sinusoidal pulsewidth modulation (PWM) pulse-rotation-control approach, for a wide range of output voltage, provides a simple way to implement vector control for IM when the cascaded NPC inverter is employed.
Abstract: For a cascaded neutral-point-clamped (NPC) inverter applied to the medium-voltage high-power induction-motor (IM) drives, an effective control technique is proposed in this paper. The novel sinusoidal pulsewidth modulation (PWM) pulse-rotation-control approach, for a wide range of output voltage, provides a simple way to implement vector control for IM when the cascaded NPC inverter is employed. The proposed method presents great benefits to the cascaded NPC inverter. The output voltages and power of all inverter modules and the two series-capacitor dc voltages of each inverter module are perfectly balanced. Moreover, a low switch frequency of all inverter modules supports a synthesized high-frequency PWM phase voltage. The internal voltage drop of the inverter, due to the cascade structure of many insulated-gate bipolar transistor-diode modules' series connection, is analyzed, which causes the distorted phase voltages and currents at low speeds when the frequency and the output voltage are low. The current closed-loop control compensates the distortion of phase voltages and currents. A rotor-flux-oriented vector control is combined with back-electromotive-force-based model reference adaptive system speed estimation, which results in a speed closed-loop control. The voltage sensors together with the filters of changeable parameters ensure the precision of speed estimation for the whole frequency range. The experimental tests are carried out through an 800-kW 4160-V IM drive fed by the 1-MVA 6000-V 17-level cascaded NPC inverter. The results verify the proposed scheme.
74 citations
"Harmonic Analysis and Controller De..." refers background in this paper
...meet the voltage rating [1]–[3] with Si IGBTs....
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...2582803 state transformers (SST) and MV drives [1]–[3]....
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12 Nov 2012
TL;DR: In this paper, a three-level neutral point clamped voltage source converter (3L-NPC VSC) was used as a 7.2kV grid interface for the solid state transformer and STATCOM operation.
Abstract: Silicon Carbide (SiC) devices and modules have been developed with high blocking voltages for Medium Voltage power electronics applications. Silicon devices do not exhibit higher blocking voltage capability due to its relatively low band gap energy compared to SiC counterparts. For the first time, 12kV SiC IGBTs have been fabricated. These devices exhibit excellent switching and static characteristics. A Three-level Neutral Point Clamped Voltage Source Converter (3L-NPC VSC) has been simulated with newly developed SiC IGBTs. This 3L-NPC Converter is used as a 7.2kV grid interface for the solid state transformer and STATCOM operation. Also a comparative study is carried out with 3L-NPC VSC simulated with 10kV SiC MOSFET and 6.5kV Silicon IGBT device data.
71 citations
"Harmonic Analysis and Controller De..." refers background in this paper
...IGBTs have lower conduction loss due to conductivity modulation in the drift region [4]....
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13 Nov 2014
Abstract: This paper presents the development of a distribution network solid state transformer (SST) based on high voltage (13kV) SiC MOSFET and JBS diode. This distribution SST is composed with a medium voltage ac/dc rectifier, medium voltage medium frequency dc/dc converter and a low voltage inverter. It's able to be interfaced to 3.6kV distribution grid and output both a 400V dc and 240/120V ac. This paper presents the characterization of the high voltage SiC MOSFET devices, and the design of rectifier and dc/dc converter. The test results of its grid-connected operation including pre-charge, start up, regeneration, etc. are included to show the functionalities of the designed SST prototype.
56 citations
"Harmonic Analysis and Controller De..." refers methods in this paper
...Single-phase gridconnected converters are discussed in [8], [9] using 10 kV SiC MOSFETS [10]....
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04 Dec 2014
TL;DR: In this paper, three unidirectional AC/DC SiC-based Solid-State Transformer (SST) topologies with direct connection to the medium-voltage (MV) grid are presented.
Abstract: 400 V DC distribution networks present a promising solution for supplying high-power DC loads such as information processing systems, transportation battery charging facilities and DC micro grids, among others. For these applications, high transmission efficiency, reliability and controllability are mandatory. With the current technology, these loads are fed from PWM rectifiers which are connected to the three-phase Low-Voltage (LV) distribution grid (400 V AC in Europe). The LV grid itself is supplied via Low-Frequency Transformers (LFT) from the Medium-Voltage (MV) grid, providing galvanic isolation and the required voltage step down. This paper presents three unidirectional AC/DC SiC-based Solid-State Transformer (SST) topologies with direct connection to the MV grid, which avoid the utilization of the aforementioned LFT by integrating a Medium-Frequency (MF) conversion stage, thus increasing the efficiency and power density of this supply system. The SST topologies are compared by means of a chip area-based comparative evaluation. Finally, the most suited among the presented topologies is Pareto-optimized, achieving a total MV AC to 400 V DC efficiency of 98.3 %. It is shown that the optimized SST features 40 % less overall losses compared to state-of-the-art solutions.
50 citations
"Harmonic Analysis and Controller De..." refers background in this paper
...7 kV silicon carbide (SiC) MOSFET based three-phase MV grid interface is proposed in [7], switching at 50 kHz....
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12 Nov 2012
TL;DR: In this article, the authors present the latest developments in ultra high voltage 4H-SiC IGBTs, including buffer layer design, which includes controlling the doping concentration and the thickness of the field-stop buffer layers.
Abstract: We present our latest developments in ultra high voltage 4H-SiC IGBTs. A 4H-SiC P-IGBT, with a chip size of 6.7 mm × 6.7 mm and an active area of 0.16 cm2 exhibited a record high blocking voltage of 15 kV, while showing a room temperature differential specific on-resistance of 24 mΩ-cm2 with a gate bias of −20 V. A 4H-SiC N-IGBT with the same area showed a blocking voltage of 12.5 kV, and demonstrated a room temperature differential specific on-resistance of 5.3 mΩ-cm2 with a gate bias of 20 V. Buffer layer design, which includes controlling the doping concentration and the thickness of the field-stop buffer layers, was used to control the charge injection from the backside. Effects on buffer layer design on static characteristics and switching behavior are reported.
43 citations