Hierarchical test generation and design for testability methods for ASPPs and ASIPs
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Cites background from "Hierarchical test generation and de..."
...Genesis [12]–[15] is an approach based on such hierarchical test generation for data paths....
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References
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"Hierarchical test generation and de..." refers methods in this paper
...We compare the performance of our method against HITEC [ 37 ], an efficient gate-level sequential test generator....
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"Hierarchical test generation and de..." refers methods in this paper
...The testing of the controller was handled separately as the controller consists of a ROM which is neither supported by SIS [ 33 ], the logic synthesis tool that we used, nor the fault simulation tool PROOFS [34] available to us. Part of the overhead calculation for the controller part of the circuit had to be done manually using instruction ROM’s generated by the ALLIANCE synthesis system [35]....
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"Hierarchical test generation and de..." refers methods in this paper
...Fig. 12 shows the RTL circuit of an ASIP named SimpleCPU, which we have taken from [ 30 ] and modified slightly to give it a little more functionality....
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