High Frequency Buck Converter Design Using Time-Based Control Techniques
01 Apr 2015-IEEE Journal of Solid-state Circuits (Institute of Electrical and Electronics Engineers Inc.)-Vol. 50, Iss: 4, pp 990-1001
TL;DR: Time-based control techniques for the design of high switching frequency buck converters are presented and eliminates the need for wide bandwidth error amplifier, pulse-width modulator (PWM) in analog controllers or high resolution analog-to-digital converter (ADC) and digital PWM in digital controllers.
Abstract: Time-based control techniques for the design of high switching frequency buck converters are presented. Using time as the processing variable, the proposed controller operates with CMOS-level digital-like signals but without adding any quantization error. A ring oscillator is used as an integrator in place of conventional opamp-RC or G $_{\rm m}$ -C integrators while a delay line is used to perform voltage to time conversion and to sum time signals. A simple flip-flop generates pulse-width modulated signal from the time-based output of the controller. Hence time-based control eliminates the need for wide bandwidth error amplifier, pulse-width modulator (PWM) in analog controllers or high resolution analog-to-digital converter (ADC) and digital PWM in digital controllers. As a result, it can be implemented in small area and with minimal power. Fabricated in a 180 nm CMOS process, the prototype buck converter occupies an active area of 0.24 mm $^{2}$ , of which the controller occupies only 0.0375 mm $^{2}$ . It operates over a wide range of switching frequencies (10–25 MHz) and regulates output to any desired voltage in the range of 0.6 V to 1.5 V with 1.8 V input voltage. With a 500 mA step in the load current, the settling time is less than 3.5 $\mu$ s and the measured reference tracking bandwidth is about 1 MHz. Better than 94% peak efficiency is achieved while consuming a quiescent current of only 2 $\mu$ A/MHz.
Citations
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TL;DR: This work explores pulse frequency modulation (PFM) that is commonly used to improve light load efficiency in voltage-mode controllers and extends its operation to time-based controllers to maintain high efficiency even in the presence of dynamic load variations.
Abstract: Time-based controllers are well suited for implementing both single- and multi-phase wide bandwidth high switching frequency pulsewidth modulation (PWM)-based dc–dc converters. They also consume very little quiescent current but their light load efficiency is severely degraded by switching losses. We explore pulse frequency modulation (PFM) that is commonly used to improve light load efficiency in voltage-mode controllers and extend its operation to time-based controllers. To maintain high efficiency even in the presence of dynamic load variations, we present techniques to perform automatic and seamless switching between PWM/PFM modes. Fabricated in a 65-nm CMOS, the prototype buck converter using the time-based PWM/PFM control achieves 90% peak efficiency and >80% efficiency over a load current range of 2–800 mA. Output voltage changes by less than 40 mV during PWM to PFM transitions.
56 citations
Cites background or methods from "High Frequency Buck Converter Desig..."
...In the PWM mode, current-controlled oscillators (CCOs) CCOF and CCOR provide integral control, whereas the current-controlled delay lines, CCDLF and CCDLR , in conjunction with the CR (CD RD) filter, implement proportional + derivative control [8]....
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...Consequently, efficiency of state-of-the-art time-based buck converters deteriorates significantly at light loads (<50 mA) [8], [9]....
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...Compared with [8], the proposed 10-MHz buck converter greatly improves light load efficiency as a result of combining the time-based PWM control with ON-time-controlled PFM....
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...A time-based controller was recently proposed as an alternative to classical voltage- and current-mode controllers to implement wide-bandwidth high FSW buck converters [8]....
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02 Mar 2017
TL;DR: Owing to the need for low power consumption, portable and wearable electronics operate at low voltages, typically below 1V, with recent designs in near- and subthreshold operation resulting in voltages down to 0.5V, motivating theneed for compact power converters capable of large conversion ratio with wide and efficient voltage regulation.
Abstract: Owing to the need for low power consumption, portable and wearable electronics operate at low voltages, typically below 1V, with recent designs in near- and subthreshold operation resulting in voltages down to 0.3 to 0.5V. Meanwhile, voltage range of the most common energy source - the Li-ion battery - is 3 to 4.2V, motivating the need for compact power converters capable of large conversion ratio with wide and efficient voltage regulation.
50 citations
Cites background from "High Frequency Buck Converter Desig..."
...It is challenging for conventional buck converters [1] to achieve high power density and efficiency at large conversion ratios, due to the large device voltage stress relative to the output....
[...]
TL;DR: In this article, a high switching frequency multi-phase buck converter architecture using a time-based compensator is presented, which obviates the need for a complex current sensing and calibration circuitry needed to implement active current sharing in an analog controller.
Abstract: A high switching frequency multi-phase buck converter architecture using a time-based compensator is presented. Efficiency degradation due to mismatch between the phases is mitigated by generating precisely matched duty-cycles by combining a time-based multi-phase generator (MPG) with a time-based PID compensator (T-PID). The proposed approach obviates the need for a complex current sensing and calibration circuitry needed to implement active current sharing in an analog controller. It also eliminates the need for a high resolution analog-to-digital converter and digital pulse width modulator needed for implementing passive current sharing in a digital controller. Fabricated in a 65 nm CMOS process, the prototype multi-phase buck converter occupies an active area of 0.32 mm $^{2}$ , of which the controller occupies only 0.04 mm $^{2}$ . The converter operates over a wide range of switching frequencies (30–70 MHz) and regulates output to any desired voltage in the range of 0.6 V to 1.5 V from 1.8 V input voltage. With a 400 mA step in the load current, the settling time is less than 0.6 $\mu$ s and the measured duty-cycle mismatch is less than 0.48%. Better than 87% peak efficiency is achieved while consuming a quiescent current of only 3 $\mu$ A/MHz.
35 citations
01 Jan 2015
TL;DR: The proposed approach obviates the need for a complex current sensing and calibration circuitry needed to implement active current sharing in an analog controller and also eliminates theneed for a high resolution analog-to-digital converter and digital pulse width modulator needed for implementing passive current shares in a digital controller.
Abstract: A high switching frequency multi-phase buck con- verter architecture using a time-based compensator is presented. Efficiency degradation due to mismatch between the phases is mit- igated by generating precisely matched duty-cycles by combining a time-based multi-phase generator (MPG) with a time-based PID compensator (T-PID). The proposed approach obviates the need for a complex current sensing and calibration circuitry needed to implement active current sharing in an analog controller. It also eliminates the need for a high resolution analog-to-digital con- verter and digital pulse width modulator needed for implementing passive current sharing in a digital controller. Fabricated in a 65 nm CMOS process, the prototype multi-phase buck converter occupies an active area of 0.32 mm , of which the controller occupies only 0.04 mm . The converter operates over a wide range of switching frequencies (30-70 MHz) and regulates output to any desired voltage in the range of 0.6 V to 1.5 V from 1.8 V input voltage. With a 400 mA step in the load current, the settling time is less than 0.6 s and the measured duty-cycle mismatch is less than 0.48%. Better than 87% peak efficiency is achieved while consuming a quiescent current of only 3 A/MHz.
31 citations
Cites background or methods from "High Frequency Buck Converter Desig..."
...This not only helps to reduce power consumption but also improves phase margin by lowering loop delay [3]....
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...The values of compensator parameters such as , , , and are calculated using the design process described in [3], and the result is shown in Table II....
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...2456884 component size (values of L and C scale inversely proportional to ) [1]–[3]....
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...The phase margin is greater than 45 degrees even in the presence of PVT variations [3]....
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...A time-based compensator that combines the good attributes of both analog and digital compensators was recently introduced [3]....
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TL;DR: The controller of a current-mode buck converter is realized by only time-domain circuits such as voltage-controlled oscillator, voltage- controlled delay line, and phase detector, which allows the switching duty cycle and thus the output voltage to be controlled in a wide range.
Abstract: The controller of a current-mode buck converter is realized by only time-domain circuits such as voltage-controlled oscillator (VCO), voltage-controlled delay line (VCDL), and phase detector (PD). The inductor current is sensed by a VCO, which helps improving power efficiency and eliminates the need for the slope compensation preventing the sub-harmonic oscillation. The type-II frequency compensation network is realized by a combination of VCO and VCDL without an error amplifier (EA) and RC network which may consume large power and occupy large silicon area. Instead of voltage comparator, a PD detects the error of the output voltage, which allows the switching duty cycle and thus the output voltage to be controlled in a wide range. With the proposed time-domain current-mode controller, a buck converter has been implemented in a 65-nm CMOS process. The output voltage can be regulated from 0.15 to 1.69 V from a 1.8-V input and the maximum load current is 0.6 A. The peak power efficiency is 94.9% when the output is 1.5 V and the load current is 250 mA. The load transient speed is better than 3.5 $\mu \text{s}$ for both the step-up and step-down changes of the load current by 480 mA in 0.1 $\mu \text{s}$ .
27 citations
Cites background or result from "High Frequency Buck Converter Desig..."
...7 to reduce the control latency by half when compared with a single-ended one [3], [16]....
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...In [3]–[5], the controllers of voltage-mode buck converters are implemented with only time-domain circuits such as voltage-controlled oscillator (VCO), voltage-controlled delay line (VCDL), and phase detector (PD)....
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...Therefore, buck converters should be capable of providing stable supply voltage even with the rapidly changing operating conditions [1]–[3]....
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TL;DR: In this article, the authors proposed a dynamic voltage scaling (DVS) strategy to achieve the highest possible energy efficiency for time-varying computational loads, which can reduce energy consumption for low computational periods while retaining peak performance when required.
Abstract: The microprocessor system in portable electronic devices often has a time-varying computational load which is comprised of: (1) compute-intensive and low-latency processes, (2) background and high-latency processes, and (3) system idle. The key design objectives for the processor systems in these applications are providing the highest possible peak performance for the compute-intensive code (e.g., handwriting recognition, image decompression) while maximizing the battery life for the remaining low performance periods. If clock frequency and supply voltage are dynamically varied in response to computational load demands, then energy consumed per process can be reduced for the low computational periods, while retaining peak performance when required. This strategy, which achieves the highest possible energy efficiency for time-varying computational loads, is called dynamic voltage scaling (DVS).
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TL;DR: In this paper, the presence of steady-state limit cycles in digitally controlled PWM converters is discussed, and conditions on the control law and quantization resolution for their elimination are suggested.
Abstract: This paper discusses the presence of steady-state limit cycles in digitally controlled pulse-width modulation (PWM) converters, and suggests conditions on the control law and the quantization resolution for their elimination. It then introduces single-phase and multi-phase controlled digital dither as a means of increasing the effective resolution of digital PWM (DPWM) modules, allowing for the use of low resolution DPWM units in high regulation accuracy applications. Bounds on the number of bits of dither that can be used in a particular converter are derived. Finally, experimental results confirming the theoretical analysis are presented.
735 citations
"High Frequency Buck Converter Desig..." refers background in this paper
...Because of the quantization error introduced by the ADC and DPWM, the converter behavior is non-linear and its steady state is a bounded limit cycle, which manifests as output voltage ripple [13]....
[...]
TL;DR: An overview of ripple-based control techniques can be found in this paper, where the authors discuss their merits and limitations, and introduce techniques for reducing the noise sensitivity and the sensitivity to capacitor parameters, improving the frequency stability and the dc regulation.
Abstract: Switching regulators with ripple-based control (ie, ?ripple regulators?) are conceptually simple, have fast transient responses to both line and load perturbations, and some versions operate with a switching frequency that is proportional to the load current under the discontinuous conduction mode These characteristics make the ripple regulators well-suited, especially for power management applications in computers and portable electronic devices Ripple regulators also have some drawbacks, including (in some versions) a poorly defined switching frequency, noise-induced jitter, inadequate dc regulation, and a tendency for fast-scale instability This paper presents an overview of the various ripple-based control techniques, discusses their merits and limitations, and introduces techniques for reducing the noise sensitivity and the sensitivity to capacitor parameters, improving the frequency stability and the dc regulation, and avoiding fast-scale instability
349 citations
TL;DR: In this paper, a dual-mode digitally controlled buck converter IC for cellular phone applications is described, which employs internal power management to ensure voltage compatibility between a single-cell lithium-ion battery voltage and a low-voltage integrated circuit technology.
Abstract: This paper describes a dual-mode digitally controlled buck converter IC for cellular phone applications. An architecture employing internal power management is introduced to ensure voltage compatibility between a single-cell lithium-ion battery voltage and a low-voltage integrated circuit technology. Special purpose analog and digital interface elements are developed. These include a ring-oscillator-based A/D converter (ring-ADC), which is nearly entirely synthesizable, is robust against switching noise, and has flexible resolution control, and a very low power ring-oscillator-multiplexer-based digital pulse-width modulation (PWM) generation module (ring-MUX DPWM). The chip, which includes an output power stage rated for 400 mA, occupies an active area 2 mm/sup 2/ in 0.25-/spl mu/m CMOS. Very high efficiencies are achieved over a load range of 0.1-400 mA. Measured quiescent current in PFM mode is 4 /spl mu/A.
242 citations