High-Frequency Resonant SEPIC Converter
With Wide Input and Output Voltage Ranges
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Citation Hu, Jingying, Anthony D. Sagneri, Juan M. Rivas, Yehui Han, Seth
M. Davis, and David J. Perreault. “High-Frequency Resonant SEPIC
Converter With Wide Input and Output Voltage Ranges.” IEEE Trans.
Power Electron. 27, no. 1 (n.d.): 189–200.
As Published http://dx.doi.org/10.1109/TPEL.2011.2149543
Publisher Institute of Electrical and Electronics Engineers (IEEE)
Version Author's final manuscript
Citable link http://hdl.handle.net/1721.1/86907
Terms of Use Creative Commons Attribution-Noncommercial-Share Alike
Detailed Terms http://creativecommons.org/licenses/by-nc-sa/4.0/
IEEE TRANSACTIONS ON POWER ELECTRONICS 1
High Frequency Resonant SEPIC Converter with
Wide Input and Output Voltage Ranges
Jingying Hu, Student Member, IEEE, Anthony D. Sagneri, Student Member, IEEE, Juan M. Rivas, Member, IEEE,
Yehui Han, Student Member, IEEE, Seth M. Davis, and David J. Perreault, Senior Member, IEEE
Abstract—This document presents a resonant Single-Ended-
Primary-Inductor-Converter (SEPIC) converter and control
method suitable for high frequency (HF) and very high frequency
(VHF) dc-dc power conversion. The proposed design features
high efficiency over a wide input and output voltage range, up-
and-down voltage conversion, small size, and excellent transient
performance. In addition, a resonant gate drive scheme is
presented which provides rapid startup and low-loss at HF and
VHF frequencies. The converter regulates the output using an
on-off control scheme modulating at a fixed frequency (170 kHz).
This control method enables fast transient response and effi-
cient light load operation while providing controlled spectral
characteristics of the input and output waveforms. A hysteretic
override technique is also introduced which enables the converter
to reject load disturbances with a bandwidth much greater than
the modulation frequency, limiting output voltage disturbances
to within a fixed value. An experimental prototype has been
built and evaluated. The prototype converter, built with two
commercial vertical MOSFETs, operates at a fixed switching
frequency of 20 MHz, with an input voltage range of 3.6 V to
7.2 V, an output voltage range of 3 V to 9 V and an output
power rating of up to 3W. The converter achieves higher than
80% efficiency across the entire input voltage range at nominal
output voltage, and maintains good efficiency across the whole
operating range.
Index Terms—Resonant dc-dc converter, quasi-resonant SEPIC
converter, high frequency, VHF integrated power converter,
class E inverter, resonant gate drive, resonant rectifier, on-off
control.
I. INTRODUCTION
M
ANY portable electronic applications could benefit
from a power converter able to achieve high efficiency
across wide input and output voltage ranges at a small size.
However, it is difficult for many conventional power converter
designs to provide wide operation range while maintaining
high efficiency, especially if both up-and-down voltage con-
version is to be achieved. Furthermore, the bulk energy storage
required at contemporary switching frequencies of a few mega-
hertz and below limits the degree of miniaturization that can
be achieved and hampers fast transient response. Therefore,
J. Hu, A. D. Sagneri and D. J. Perreault are with the Department of Elec-
trical Engineering and Computer Science, Massachusetts Institute of Tech-
nology, Cambridge, MA 02139 USA (email: jyh@mit.edu, sagnea@mit.edu,
djperrea@mit.edu).
J. M. Rivas is with GE Global Research, Niskayuna, NY 12309 USA (email:
rivasd@ge.com).
Y. Han is with the Department of Electrical Engineering and Com-
puter Science, University of Wisconsin-Madison, WI 02139 USA (email:
yehui@engr.wisc.edu).
S. M. Davis is with the Charles Stark Draper Laboratory, Cambridge, MA
02139 USA (email: sethd@draper.com).
design methods that reduce energy storage requirements and
expand efficient operation range are desirable. In this paper,
we exploit the use of resonant switching and gating along with
fixed frequency control techniques to achieve these goals.
This paper introduces a quasi-resonant SEPIC converter,
resonant gate drive and associated control methods suitable for
converter designs at frequencies above 10 MHz. Unlike many
resonant converter designs [1]–[4], the proposed approach
provides high efficiency over very wide input and output
voltage ranges and power levels. It also provides up-and-
down conversion, and requires little energy storage which
allows for excellent transient response. Unlike conventional
quasi-resonant and multi-resonant converters [3], [4], no bulk
inductor is used and the converter operates at fixed frequency
and duty ratio. These attributes reduce passive component
size, improve response speed, and enable the use of low-
loss sinusoidal resonant gating. Furthermore, a new fixed-
frequency on/off control is introduced which provides good
control over input and output frequency content. The proposed
design is discussed in the context of a prototype converter
operating over wide input voltage (3.6− 7.2V), output voltage
(3 − 9 V) and power (0.3 − 3 W) ranges. This design is
suitable, for example, for a power supply to provide adaptive
bias control of an RF power amplifier from a battery input.
The wide output voltage and power reflect the requirements
for adjusting bias to the power amplifier, while the wide input
voltage reflects operation from a battery pack across the charge
and discharge range. Section II presents the new proposed
circuit design and discusses its operation. A low-loss resonant
gate drive method suitable for this application is explained in
detail in Section III, followed by a discussion of the converter
control scheme in Section IV. Section V presents the design
and experimental validation of a converter implementing the
approach.
II. A NEW RESONANT SEPIC CONVERTER
Figure 1 shows the power stage of the proposed converter.
The topology used here has some topological similarities
with both the conventional SEPIC converter [5] and with the
multi-resonant SEPIC converter proposed in [4]. However, the
detailed component placement and sizing, operating character-
istics, and control approach are all very different from previous
designs.
First, consider the circuit topology. The conventional SEPIC
converter has two bulk (ac choke) inductors, and yields hard
switching of the switch and diode. Thus, in the conventional
Vol. 27, No. 1, pp. 189-200, Jan. 2012.
IEEE TRANSACTIONS ON POWER ELECTRONICS 2
+
−
+
−
M
1
C
EX
C
EX2
D
1
C
S
L
RS
L
F
V
IN
V
OUT
+
_
+
-
V
DS
V
R
C
IN
C
OUT
Fig. 1. Schematic of the proposed resonant SEPIC converter topology.
quasi-resonant SEPIC converter L
F
is a choke inductor, se-
lected to provide nearly constant current over a switching
cycle. The multi-resonant SEPIC [4] utilizes similar bulk
inductors, but explicitly introduces capacitances in parallel
with the switch and diode along with a resonant inductor in
series with the coupling capacitor C
S
to achieve zero-voltage
soft switching of the switch and diode. The design introduced
here also explicitly utilizes capacitances in parallel with the
switch and diode. However, in contrast to previous resonant
SEPIC designs [3], [4], the design here has no bulk inductors.
Rather, it uses only two resonant inductors: one inductor, L
F
,
resonates with the net switch capacitance, C
OSS
+C
EX
, for
resonant inversion, while the other inductor, L
RS
, resonates
with the rectifier capacitance, C
EX2
, for resonant rectification.
This design method leads to reduced magnetic component
count, along with greatly increased response speed.
A further major difference between the converter proposed
here and previous resonant SEPIC converters relates to control.
The conventional resonant SEPIC converter regulates the out-
put voltage by keeping the on-time pulse fixed while varying
the off time duration, leading to variable-frequency, variable-
duty-ratio operation. Unlike conventional designs which used
variable frequency control to regulate the output [3], [4], the
design here operates at fixed switching frequency and duty
ratio. (As discussed in Section IV, output control is instead
achieved through on/off control, in which the entire converter
is modulated on and off at a modulation frequency that is
far below the switching frequency [6]–[13].) Operation at
a fixed frequency and duty ratio enables the elimination of
bulk magnetic components (as described above) and facilitates
the use of highly efficient sinusoidal resonant gating (as
described in Section IV). Moreover, it enables zero-voltage
soft switching to be maintained over wide input and output
voltage ranges, and eliminates the variation in device stress
with converter load that occurs in many resonant designs [3],
[4].
Operation of this converter can be understood as a linking
of two subsystems: a resonant inverter and a resonant rectifier.
The design procedure for the proposed topology involves
designing the rectifier and inverter individually, coupling the
inverter and rectifier together, then retuning as necessary to
account for nonlinear interactions between the inverter and
rectifier. We treat these steps in the following subsections.
A. Rectifier Design
The design procedure of a full dc-dc converter starts with the
rectifier. The particular resonant rectifier topology of interest
+
−
I
IN
L
R
D
1
C
EX2
C
OUT
V
OUT
+
_
V
R
Fig. 2. Circuit model for tuning of the resonant rectifier.
here is illustrated in Fig. 2 (along with a sinusoidal drive
source used in tuning the rectifier design). A similar rectifier
structure was exploited in [7] but under different driving
conditions. The rectifier utilizes a resonant tank comprising a
resonant inductor L
R
(which provides a dc path for the output
current) and a capacitance including an external capacitor
C
EX2
along with additional parasitic junction capacitance
from the diode.
To design the rectifier, we start by assuming that it is
driven by a sinusoidal current source of magnitude I
IN
at
a given output voltage V
OU T
, as illustrated in Fig. 2. (It is
recognized that the actual drive waveform is not sinusoidal;
this fact is addressed in a later tuning step.) For a desired
output power level and operating frequency, the rectifier is
tuned to appear resistive in a describing function sense by
adjusting C
EX2
and L
R
. That is, we adjust C
EX2
and L
R
such that the fundamental component of V
R
is in phase with
the drive waveform I
IN
(or alternatively has some phase
shift, thus presenting an equivalent reactive component.) In
doing this, we start by assuming a drive amplitude I
IN
. We
also adjust the values of L
R
and C
EX2
and/or the assumed
drive level I
IN
to ensure that the desired power is delivered
through the rectifier. The equivalent rectifier impedance at
the operating frequency is calculated as the complex ratio
Z
EQV
= V
R,1
/I
IN
, where V
R,1
is the fundamental of V
R
.
This equivalent impedance can be used in place of the rectifier
for designing the resonant inverter, assuming that the majority
of the output power delivered to the load is transferred through
the fundamental.
The following design example of a 4 W rectifier at a
nominal output voltage of 7 V illustrates the tuning procedure
described above. The rectifier uses a commercial Schottky
diode DFLS230L (having an approximate capacitance of
70 pF) and is driven by a sinusoidal current source I
IN
with
an amplitude of 0.7A. The value of L
R
of the resonant rectifier
is selected in conjunction with C
EX2
so that the fundamental
rectifier input voltage V
R
is in phase with rectifier input current
I
IN
. Figure 3 shows the input current and voltage of a resonant
rectifier (like the one in Fig. 2) simulated using PSPICE.
For the simulation shown, L
R
= 118 nH, C
EX2
= 150 pF,
V
OU T
= 7 V, and the sinusoidal input current I
IN
= 0.7 A
at a frequency of 20 MHz. The average power delivered to
the load under these conditions is 4.12 W. In Fig. 3, the
fundamental component of the input voltage and the current
are in phase resulting in a rectifier with an equivalent resistance
(at the fundamental) of approximately 17.14 Ω. As the values
of L
R
and C
EX2
are changed, output power level and the
Vol. 27, No. 1, pp. 189-200, Jan. 2012.
IEEE TRANSACTIONS ON POWER ELECTRONICS 3
14.82 14.84 14.86 14.88 14.9 14.92 14.94
−25
−20
−15
−10
−5
0
5
10
15
20
Rectifier Voltage and Current
time [us]
Amplitude [V] (or [A])
Fundamental Rectifer Current x 10
Fundamental Rectifer Voltage
Rectifer Voltage
Fig. 3. Fundamentals of rectifier voltage, V
R
and current, I
IN
of the resonant
rectifier of Fig. 2 tuned to look resistive at an operating frequency of 20 MHz.
Simulation is for a rectifier built with a DFLS230L Schottky diode, L
R
=
118 nH, C
EX2
= 150 pF, and V
OU T
= 7 V.
TABLE I
TUNED AND DETUNED RECTIFIER COMPONENT VALUES
L
R
90 nH 118 nH 118 nH
C
EX2
150 pF 50 pF 150 pF
|Z
EQV
| 18.07 Ω 19.08 Ω 18.12 Ω
∠Z
EQV
36.9
◦
47.69
◦
0
P
OU T
2.28 W 2.97 W 4.12 W
Efficiency 89.6% 90.6% 91.4%
phase relationship between V
R
and I
IN
change. As the phase
difference between V
R
and I
IN
increases, the losses due
to reactive currents rise, reducing the output power and the
overall efficiency of the rectifier, as shown in Table I.
B. Inverter Design
Consider the inverter network of Fig. 4, which includes
impedance matching from the inverter to the equivalent recti-
fier impedance. Inverter tuning begins by selecting appropriate
matching components. (The matching inductance is later ab-
sorbed as part of the rectifier, with L
RS
being the parallel
combination of the inverter inductor L
S
and the rectifier
inductor L
R
.)
Assuming that most power is transferred through the fun-
damental, the maximum equivalent resistance R
MAX
needed
to deliver an output power level of P
OU T
with a fundamen-
tal voltage at the MOSFET drain, V
DS,1
can be calculated
from R
MAX
= V
2
DS,1
/(2 ∗ P
OU T
),where R
MAX
is the
“transformed” resistance loading the drain-to-source port of
the inverter. As Fig. 5 illustrates, the drain waveform of the
resonant SEPIC converter is similar to that of a conventional
Class-E inverter. Therefore, one possible starting point to
obtain R
MAX
is to approximate the fundamental voltage as
in the Class-E inverter case, V
DS,1
= 1.6 ∗ V
IN
, [14]. (It
is recognized that the actual V
DS,1
of the resonant SEPIC
converter is not exactly 1.6 ∗ V
IN
, the effects of which can
be addressed by adjusting output power when coupling the
inverter and rectifier together.)
+
−
R
EQV
C
F
L
F
L
S
C
S
V
IN
Fig. 4. Resonant inverter including a matching circuit and equivalent load
resistance. This circuit model is used for tuning the inverter.
3.52 3.54 3.56 3.58 3.6 3.62
−25
−20
−15
−10
−5
0
5
10
15
20
25
30
Drain and Rectifier Voltage, Nominal Vout
time [us]
Voltage [V]
Vin=3.6V
Vin=5.4V
Vin=7.2V
DRAIN
RECTIFIER
Fig. 5. Simulated drain (V
DS
) and rectifier (V
R
) voltages for a 20 MHz
converter operating with V
out
= 7 V, L
F
= 22 nH, C
EX
= 780 pF,
C
EX2
= 100 pF, C
S
= 1270 pF, and L
P
= 41 nH. Inductor Q of
70 and capacitor Q of 3000 is assumed. Two SP N1443 MOSFETs and
a DF LS230L diode are used.
When the rectifier equivalent resistance, R
EQV
, is higher
than the value R
MAX
to meet the output power requirement,
a matching network consisting of L
S
and C
S
is required
to transform the load impedance to a lower value [7], [15],
[16]. The approximate transformation ratio can be obtained
as R
MAX
/R
EQV
. One possible starting point to selecting
the component values for L
S
and C
S
is to design a match-
ing network such that a transformation ratio R
MAX
/R
EQV
occurs at the desired operating frequency. Additional minor
adjustments on these component values may be done later in
conjunction with tuning C
F
and L
F
with a simulation tool
(e.g. PSPICE) to achieve a resulting drain-to-source switching
waveform V
DS
that has ZVS and zero dv/dt at turn on. In
practice, the resonance of L
S
and C
S
can be set to be exactly
at the switching frequency, or slightly above or below the
resonant frequency, all of which are typically viable and will
lead to a working design. In a given application, one tuning
may result in more achievable component values and therefore
may be more favorable compared to the others. Once matching
network components have been selected, inductance L
S
may
be absorbed into the rectifier inductance L
R
.
The input resonant network, comprising L
F
and C
F
, largely
shapes the frequency at which the drain waveform rings up
and down. For an inverter operating at a 50% duty ratio, one
possible starting point for L
F
is to tune the input resonant
Vol. 27, No. 1, pp. 189-200, Jan. 2012.
IEEE TRANSACTIONS ON POWER ELECTRONICS 4
network such that its resonance frequency is at twice the
switching frequency, as in (1). This tuning selection is similar
to that of the “second harmonic” class E inverter in [17], [18].
L
F
=
1
16π
2
f
2
SW
C
F
(1)
Note that the capacitor C
F
includes the parasitic capacitance
of the semiconductor switch and possibly an external capacitor
C
EX
. In some applications where the packaging inductance
of the semiconductor switch is significant, selecting C
F
to
be solely provided by the device capacitance may be a good
choice, because it prevents waveform distortion caused by
additional ringing between the external capacitance and the
package inductance. In other cases where the circulating
current is significant, it is a better choice to add additional
high-Q ceramic capacitance in parallel with the lossy device
parasitic capacitance to reduce the circulating current loss. One
starting point for C
F
is to assume it is comprised solely of
parasitic capacitance of the semiconductor switch, allowing
an initial value of L
F
to be calculated. Since L
F
significantly
impacts the transient response speed, a small L
F
is generally
preferred. If the starting point of C
F
leads to too large a value
of L
F
, additional parallel capacitance C
EX
may be added until
the value of L
F
is in the desired range.
Once the initial values of L
F
, C
F
, L
S
and C
S
are de-
termined from the procedure above, additional tuning can be
made via minor adjustments of the component values along
with the duty ratio until the resulting drain-to-source switching
waveform V
DS
achieves ZVS and zero dv/dt turn on, the so-
called class E switching waveform.
Using the equivalent resistance R
EQV
= 17.14 Ω from
the rectifier design discussed previously, a 20 MHz inverter
utilizing two commercial vertical MOSFETs SP N1443 in
parallel can be designed in the following manner: a matching
network which transforms the equivalent rectifier impedance
from 17.14 Ω to 4 Ω at about the operating frequency is
required in order to deliver 4 W at an input voltage of 3.6 V.
The component values for such a matching network are
L
S
= 76nH and C
S
= 1120pF. If C
F
is to be comprised solely
of the parasitic capacitance of SP N1443 (about 160 pF), the
resulting L
F
is about 141 nH, a condition which deteriorates
the transient response speed and overall closed-loop efficiency.
In this design, it is found through time-domain simulations that
it is desirable to add additional high-Q ceramic capacitance in
parallel with the lossy device parasitic capacitance to reduce
the overall loss and to reduce the component value (and size)
of the input inductor L
F
. A starting value for L
F
is chosen to
be 22 nH (so that the inductance is small enough to allow for
fast transient response and large enough to not be significantly
affected by low-Q board parasitic inductance), resulting in an
external capacitor C
EX
of 550 pF at a 50% duty ratio.
C. dc/dc Retuning
An entire converter design may be accomplished by con-
necting the tuned inverter to the resonant rectifier. When the
inverter and rectifier are connected, the circuit waveforms and
the output power level may be slightly different than that pre-
dicted by the inverter loaded with the equivalent impedance,
ENABLE
L
S
L
P
D
2
M
3
U
1
U
2
x 8
U
3
C
P
C
GD
C
GS
Rg
Fig. 6. Resonant sinusoidal gate drive circuit with MOSFET gate model.
due to the non-linear interaction between the inverter/matching
network with the rectifier. Minor additional tuning may thus
be required to achieve ZVS and the required power level. The
final component values for a complete converter using the
example rectifier and inverter design described in this section
will be presented in Section V. A complete discussion of the
tuning methodology for these components is found in [19].
Figure 5 shows the idealized drain and rectifier voltage
waveforms for the proposed design over a range of input volt-
ages using the techniques outlined in previous subsections (the
component values are included in the description of Fig. 5). It
can be seen that zero-voltage soft switching is achieved at fixed
frequency and duty ratio across a wide range of input voltages.
In addition, while developing the design required tuning of
the selected circuit component values, this tuning needed
only to be performed once. The converter performance was
found to be repeatable across several prototypes. Moreover,
the converter is tolerant of the device non-linear capacitance
variation with input voltage over the entire operating range.
III. GATE DRIVER
At HF and VHF frequencies, traditional hard-switched gate
drives typically incur too much loss for acceptable efficiency,
especially for low power converters. Resonant gating can
reduce the gating loss significantly at these frequencies [7]–[9],
[20]. By recovering a portion of the gate energy each cycle,
much lower power is required to drive the gate, minimizing
the impact that gating loss has on overall converter efficiency.
While use of fixed-frequency and fixed-duty-ratio operation
reduces driver complexity, the use of on-off control of the
output introduces some important requirements. In addition
to achieving low power operation at steady state, a practi-
cal gate drive for our system must settle rapidly at startup
and shutdown to maintain good converter transient response
and high efficiency under modulation. A low-loss gate drive
method is designed to meet these criteria for this converter.
Figure 6 shows a schematic of the resonant driver circuit we
have adopted. The detailed design approach and the operation
of the gate drive is summarized as follows:
In the driver of Fig. 6, a bank of CMOS inverters drives
the gate via a tuned resonant network. The shunt branch of
L
P
and C
P
is inductive at the switching frequency (with
C
P
simply acting as a dc block). L
P
is sized to partially
cancel the gate admittance, leaving the parallel combination
Vol. 27, No. 1, pp. 189-200, Jan. 2012.
