High performance 14nm SOI FinFET CMOS technology with 0.0174µm 2 embedded DRAM and 15 levels of Cu metallization
IBM1
01 Dec 2014-
TL;DR: In this article, the authors present a fully integrated 14nm CMOS technology featuring fin-FET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs.
Abstract: We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generation deep trench embedded DRAM to provide an ultra-dense (0.0174um2) memory solution for industry leading ‘scale-out’ processor design. A broad range of Vts is enabled on chip through a unique dual workfunction process applied to both NFETs and PFETs. This enables simultaneous optimization of both lowVt (HP) and HiVt (LP) devices without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The SOI finFET's excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (>35%) performance gain for Vdd ∼0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for ‘scale-up’ enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm2 SoCs.
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TL;DR: A high density, low-power standard cell architecture, developed using design/technology co-optimization (DTCO), as well as example SRAM cells are shown, and the PDK transistor electrical assumptions are explained, as are the FEOL and BEOL design rules.
326 citations
29 Mar 2015
TL;DR: The proposed cell library is intended to provide access to advanced technology node for universities and other research institutions, in order to design digital integrated circuits and also to develop cell-based design flows, EDA tools and associated algorithms.
Abstract: This paper presents the 15nm FinFET-based Open Cell Library (OCL) and describes the challenges in the methodology while designing a standard cell library for such advanced technology node The 15nm OCL is based on a generic predictive state-of-the-art technology node The proposed cell library is intended to provide access to advanced technology node for universities and other research institutions, in order to design digital integrated circuits and also to develop cell-based design flows, EDA tools and associated algorithms Developing a 15nm standard cell library brings out design challenges which are not present in previous technology nodes Some of these challenges include double-patterning for both metal and poly layers, a very restrictive set of physical design rules, and the demand for lithography-friendly patterns This paper discusses the development of the library considering the challenges associated with advanced technology nodes
194 citations
TL;DR: In this paper, the integration strategy of electronic and photonic ICs, 300mm process flow, and process variability are discussed, and performances of the passive and active optical devices are shown.
Abstract: Industrial implementation of a silicon photonics platform using 300-mm SOI wafers and aiming at 100 Gb/s aggregate data-rate application is demonstrated. The integration strategy of electronic and photonic ICs, 300-mm process flow, and process variability are discussed, and performances of the passive and active optical devices are shown. An example of a low-cost LGA-based package together with a fiber assembly is given. RX and TX circuits operating at 25 Gb/s are demonstrated. Finally, the process evolution toward the integration of the backside reflector and multiple silicon etching level is demonstrated.
102 citations
Additional excerpts
...architecture such as SOI-FinFETs [10] (Tsi<0....
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...Also, the thickness of the Si film can greatly differ between Si-Photonics (0.2–0.5 μm) and some CMOS device architecture such as SOI-FinFETs [10] (Tsi 0.1 μm) or UTBBSOI (Tsi 10 nm)....
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TL;DR: In this article, a survey of the state-of-the-art software-defined radio (SDR) platforms in the context of wireless communication protocols is presented, with a focus on programmability, flexibility, portability, and energy efficiency.
91 citations
30 Oct 2015
TL;DR: The core model is updated with a new unified FinFET model, which calculates charges and currents of transistors with complex fin cross-sections and threshold voltage modulation from bulk-bias effects and bias dependent quantum mechanical confinement effects are incorporated into the new core model.
Abstract: This work presents new compact models that capture advanced physical effects presented in industry FinFETs. The presented models are introduced into the industry standard compact model BSIM-CMG. The core model is updated with a new unified FinFET model, which calculates charges and currents of transistors with complex fin cross-sections. In addition, threshold voltage modulation from bulk-bias effects and bias dependent quantum mechanical confinement effects are incorporated into the new core model. Short channel effects, affecting threshold voltage and subhtreshold swing, are modeled with a new unified field penetration length, enabling accurate 14nm node FinFET modeling. The new proposed models further assure the BSIM-CMG model's capabilities for circuit design using FinFET transistors for advanced technology nodes.
66 citations
Additional excerpts
...1) has been adopted in all sub-20nm IC technologies [2]–[5] as a replacement of the conventional bulk planar technology....
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