Journal ArticleDOI
High performance compact energy efficient error tolerant adders and multipliers for 16-bit image processing applications
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TLDR
To achieve area and energy efficiency, Simplified gate level Approximate Full Adders (SAFAs) are proposed in the inaccurate part of the CEETA and CEETA1 designs and the proposed HPETM1 has a significant amount of power and area savings.About:
This article is published in Microprocessors and Microsystems.The article was published on 2020-10-01. It has received 22 citations till now. The article focuses on the topics: Adder & Gate count.read more
Citations
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Journal ArticleDOI
A Novel Random Error Approximate Adder-Based Lightweight Medical Image Encryption Scheme for Secure Remote Monitoring of Health Data
Nagarajan Manikandan,Rajappa Muthaiah,Yuvaraja Teekaraman,Ramya Kuppusamy,Arun Radhakrishnan +4 more
TL;DR: In this paper, a lightweight, secure medical image encryption scheme for the remote monitoring of health data is proposed, which uses computationally less complex weighted shift approximate adder (WSAA)-based encryption logic.
Journal ArticleDOI
High-Performance Carry Select Adders
TL;DR: This research article proposes high-performance square-root carry select adder architectures with high speed, area and energy efficiency when compared to the existing SQRT CSLA architectures by incorporating a carry enable binary to excess-1 converter (CEBEC) design that exploits a new logic optimization on the carry propagation path.
Journal ArticleDOI
Logistics management inventory model based on 5G Network and Internet of Things system
TL;DR: A useful guide for future planners of information, will be responsible for establishing a network of logistics management and development of things arising from information suppliers.
Journal ArticleDOI
High-performance and low-energy approximate full adder design for error-resilient image processing
TL;DR: In this paper, the main building block of larger arithmetic circuits and often is placed along their critical path, therefore, it is a vital task to design high-performance and low-energy Full Adder cell.
Proceedings ArticleDOI
Identifying Metrics for an IoT Performance Estimation Framework
TL;DR: In this article, the authors introduce a framework to support design decisions for heterogeneous IoT platforms and devices, where specific factors that affect the performance of devices are identified and formulated in a metric form.
References
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Book
Vlsi Digital Signal Processing Systems: Design And Implementation
TL;DR: This book discusses Digital Signal Processing Systems, Pipelining and Parallel Processing, Synchronous, Wave, and Asynchronous Pipelines, and Bit-Level Arithmetic Architectures.
Journal ArticleDOI
Low-Power Digital Signal Processing Using Approximate Adders
TL;DR: This paper proposes logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy, and demonstrates the utility of these approximate adders in two digital signal processing architectures with specific quality constraints.
Journal ArticleDOI
Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications
TL;DR: It is shown that these proposed Bio-inspired Imprecise Computational blocks (BICs) can be exploited to efficiently implement a three-layer face recognition neural network and the hardware defuzzification block of a fuzzy processor.
Journal ArticleDOI
Design and Analysis of Approximate Compressors for Multiplication
TL;DR: The results show that the proposed designs accomplish significant reductions in power dissipation, delay and transistor count compared to an exact design; moreover, two of the proposed multiplier designs provide excellent capabilities for image multiplication with respect to average normalized error distance and peak signal-to-noise ratio.
Journal ArticleDOI
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing
TL;DR: A novel error-tolerant adder (ETA) is proposed that is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance.
Related Papers (5)
High-performance and energy-efficient approximate multiplier for error-tolerant applications
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