High Performance Error Tolerant Adders for Image Processing Applications

Abstract: Compact design is an extremely important criterion in the recent development error tolerant applications based on the high performance processor core The performance of the processor core depends upon the data processing sub-system architectures Area, delay and power reduction in the cost of accuracy have become the critical requirement of high quantity data computing Very Large Scale Integration (VLSI) architectures In this paper, we proposed Compact Energy efficient Error Tolerant Adders (CEETAs) which have efficient design metrics for data intensive applications To achieve area and energy efficiency, Simplified gate level Approximate Full Adders (SAFAs) are proposed in the inaccurate part of the CEETA and CEETA1 designs The simulation result shows that the proposed SAFAs based CEETA1 adder exhibits low power consumption, less Power-Delay Product (PDP), less Area-Delay Product (ADP) and it offers a savings of 5163%, 4387%, 4857%, 3652%, 3684%, 1572%, 1818% area than the conventional CSLA, SAET-CSLA, ETCSLA, HSETA, HSSSA, HPETA-I, HPETA-II, respectively Further, the Simplified Approximate Full Adders (SAFA1E and SAFA2E), 4-2 Approximate Compressor (AC) modules based High Performance Error Tolerant Multipliers (HPETMs) are proposed for error tolerant applications To achieve energy and area efficiency with high speed for the high quantity digital data computation, the propagation delay and the gate count reduction on the carry generation path are proposed in the SAFA and AC designs The proposed HPETM1 has a significant amount of power and area savings and it exhibits 2495%, 2987%, 3041%, 3179%, 3168%, 3387%, and 3558% lesser delay than the existing AM1, AM2, SSM, ACM1, ACM2, ACM3 and CDM respectively

Abstract: This research proposes a high-performance Carry Select Approximate Full Adder (CSAFA) with one error out of the eight possible output cases for high accuracy 8-bit pixel depth image processing applications. The logic optimization of the proposed CSAFA module is based on a structural hierarchy of AND-OR logic and multiplexer based pre-computation selection logic which reduces the critical path switching activity. The proposed method has the advantage of higher speed, lower power consumption and improved area efficiency. Simulation results show that the proposed CSAFA reduces the critical path delay, power consumption, area, Power-Delay Product (PDP) and Area-Delay Product (ADP) by 26.81%, 44.99%, 23.53%, 59.74%, 44.03% respectively, compared to the existing Conventional Full Adder (CFA). Further, the proposed structure incorporates the 8-bit Error Tolerant Adder (ETA-CSAFA and ETA-CSAFA1) designs. When comparing with 99.5992% Computational Accuracy (CA), the proposed ETA-CSAFA1 design exhibits 0.26% less CA and it offers a savings of 27.82% PDP and 34.39% ADP with respect to the existing ETA-2LOA architecture. The results can be substantiated with an example, a 4-bit accurate part based ETA-CSAFA1 implemented with the proposed approach almost achieves the same CA, while simultaneously reducing the power consumption by 18.14% with respect to the existing best 6-bit accurate part based ETA-2LOA architecture for 8-bit image processing applications.

Abstract: Approximate computing is a striking approach to design area-efficient low-power datapath units for fault buoyant applications. This brief presents the design of a novel 4: 2 approximate compressor that generates no error in the carry signal. The proposed compressor is employed for partial product (PP) compression in two variants of Dadda multiplier to see its effectiveness in error-resilient image and signal processing applications. In the targeted multipliers, the approximate 4:2 compressor is used in the least n PP columns, while the exact counterpart is used in the remaining most significant columns, and hence the maximum error is precisely maintained within 2n. PP compression is performed in stages using the Wallace approach, and the final two rows of sum and carry signals are added using a ripple carry adder in the basic design. In the proposed multiplier design-2, we do not generate sum bits in the approximate part. However, the proposed error-tolerant compressor is used in appropriate columns to propagate carry to the least significant column in the exact part. Performance evaluations using Cadence Encounter with 90 nm application specific integrated circuit technology revealed that the proposed-full width (P-FW) and the proposed-truncated (P-Trun) approximate multipliers demonstrate 22.7% and 32.4% power-delay product reduction compared to the standard multiplier. Implementations of the proposed multipliers in signal and image processing applications revealed superior performance in terms of accuracy compared to prior similar approximate designs.

Abstract: Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. We design architectures for video and image compression algorithms using the proposed approximate arithmetic units and evaluate them to demonstrate the efficacy of our approach. We also derive simple mathematical models for error and power consumption of these approximate adders. Furthermore, we demonstrate the utility of these approximate adders in two digital signal processing architectures (discrete cosine transform and finite impulse response filter) with specific quality constraints. Simulation results indicate up to 69% power savings using the proposed approximate adders, when compared to existing implementations using accurate adders.

Abstract: The conventional digital hardware computational blocks with different structures are designed to compute the precise results of the assigned calculations. The main contribution of our proposed Bio-inspired Imprecise Computational blocks (BICs) is that they are designed to provide an applicable estimation of the result instead of its precise value at a lower cost. These novel structures are more efficient in terms of area, speed, and power consumption with respect to their precise rivals. Complete descriptions of sample BIC adder and multiplier structures as well as their error behaviors and synthesis results are introduced in this paper. It is then shown that these BIC structures can be exploited to efficiently implement a three-layer face recognition neural network and the hardware defuzzification block of a fuzzy processor.

Abstract: In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain more than 65% improvement in the Power-Delay Product (PDP). One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors.

Abstract: Current microprocessors employ a global timing reference to synchronize data transfer. A synchronous system must know the maximum time needed to compute a function, but a circuit usually finishes computation earlier than the worst-case delay. The system nevertheless waits for the maximum time bound to guarantee a correct result. As a first step in achieving variable pipeline delays based on data values, approximation circuits can increase clock frequency by reducing the number of cycles a function requires. Instead of implementing the complete logic function, a simplified circuit mimics it using rough calculations to predict results. The results are correct most of the time, and simulations show improvements in overall performance in spite of the overhead needed to recover from mistakes.

Abstract: Power dissipation has become a significant issue for integrated circuit design in nanometric CMOS technology To reduce power consumption, approximate implementations of a circuit have been considered as a potential solution for applications in which strict exactness is not required In inexact computing, power reduction is achieved through the relaxation of the often demanding requirement of accuracy In this paper, new approximate adders are proposed for low-power imprecise applications These adders are based on XOR/XNOR gates with multiplexers implemented by pass transistors The proposed approximate XOR/XNOR-based adders (AXAs) are evaluated and compared with respect to energy consumption, delay, area and power delay product (PDP) with an accurate full adder The metric of error distance is used to evaluate the reliability of the approximate designs Simulation by Cadence's Spectre in TSMC 65nm process has shown that the proposed designs consume less power and have better performance (such as a lower propagation delay) compared to the accurate XOR/XNOR-based adder, while the error distance remains similar or better than other approximate adder designs