High Performance Four Segment Error Tolerant Adder for 8-bit Pixel Depth Image Processing Applications
TL;DR: This research proposes a high-performance Carry Select Approximate Full Adder with one error out of the eight possible output cases for high accuracy 8-bit pixel depth image processing applications and offers a savings of 27.82% PDP and 34.39% ADP with respect to the existing ETA-2LOA architecture.
Abstract: This research proposes a high-performance Carry Select Approximate Full Adder (CSAFA) with one error out of the eight possible output cases for high accuracy 8-bit pixel depth image processing applications. The logic optimization of the proposed CSAFA module is based on a structural hierarchy of AND-OR logic and multiplexer based pre-computation selection logic which reduces the critical path switching activity. The proposed method has the advantage of higher speed, lower power consumption and improved area efficiency. Simulation results show that the proposed CSAFA reduces the critical path delay, power consumption, area, Power-Delay Product (PDP) and Area-Delay Product (ADP) by 26.81%, 44.99%, 23.53%, 59.74%, 44.03% respectively, compared to the existing Conventional Full Adder (CFA). Further, the proposed structure incorporates the 8-bit Error Tolerant Adder (ETA-CSAFA and ETA-CSAFA1) designs. When comparing with 99.5992% Computational Accuracy (CA), the proposed ETA-CSAFA1 design exhibits 0.26% less CA and it offers a savings of 27.82% PDP and 34.39% ADP with respect to the existing ETA-2LOA architecture. The results can be substantiated with an example, a 4-bit accurate part based ETA-CSAFA1 implemented with the proposed approach almost achieves the same CA, while simultaneously reducing the power consumption by 18.14% with respect to the existing best 6-bit accurate part based ETA-2LOA architecture for 8-bit image processing applications.
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TL;DR: This research article proposes high-performance square-root carry select adder architectures with high speed, area and energy efficiency when compared to the existing SQRT CSLA architectures by incorporating a carry enable binary to excess-1 converter (CEBEC) design that exploits a new logic optimization on the carry propagation path.
Abstract: This research article proposes high-performance square-root carry select adder (SQRT CSLA) architectures with high speed, area and energy efficiency when compared to the existing SQRT CSLA architectures. The first proposed method uses an optimized design of binary to excess-1 converter (BEC)-based SQRT CSLA by incorporating a carry enable binary to excess-1 converter (CEBEC) design that exploits a new logic optimization on the carry propagation path to improve speed of operation, area and energy efficiency. The second proposed method is an optimized design of the regular SQRT CSLA by employing the carry enable and add-one ripple carry adder (ARCA) architectures to decrease the number of gates. Simulation results show that the proposed CEBEC SQRT CSLA offers a savings of 22.81%, 9.95%, 7.95% and 3.98% on area, 14.50%, 5.21%, 3.72% and 3.11% in power consumption and offers 6.78%, 15.46%, 6.57% and 3.83% lesser delay, 20.33%, 19.92%, 10.09% and 6.89% lesser PDP, 28%, 23.85%, 13.78% and 7.58% lesser ADP than the existing regular, BEC SQRT CSLA, SQRT CSLA1 and SQRT CSLA2 architectures. The proposed ARCA SQRT CSLA architecture exhibits 9.26%, 17.71%, 9.06% and 6.39% lesser delay than the existing regular, BEC SQRT CSLA, SQRT CSLA1 and SQRT CSLA2 architectures.
4 citations
TL;DR: This work presents three base adders using the novel concept of error tolerance in digital VLSI design that exhibit reduced delay, power dissipation, area, powerdelay product (PDP), energy delay product (EDP), and area delay product(ADP) compared to the existing approximate adders.
Abstract: The hardware implementation of error-tolerant adders using the paradigm of approximate computing has considerably influenced the performance metrics, especially in applications that can compromise accuracy. The foundation for approximate processing is the inclusion of errors in the design to enhance the effectiveness and reduce the complexity. This work presents three base adders using the novel concept of error tolerance in digital VLSI design. The research is extended to construct nine variants of power and delay-efficient 16 and 32-bit error-tolerant carry select adders (CSLA). To attain optimization in power and delay, conventional CSLA is refined by substituting ripple carry adders (RCA) with the newly proposed selector unit to minimize the switching activity. The research work includes the power, area, and delay estimates of the design from synthesis using the gpdk-90 nm and gpdk-45 nm standard cell libraries. The proposed adders exhibit reduced delay, power dissipation, area, power delay product (PDP), energy delay product (EDP), and area delay product (ADP) compared to the existing approximate adders. The proposed adder is used in an image blending application. There is a significant improvement in the peak-signal-to-noise ratio (PSNR) in the blended image compared to the standard designs.
1 citations
TL;DR: In this paper, the authors proposed a 16-bit HPVARA and HPETA-III architectures for hybrid and error tolerant applications, which are used extensively in many computing architectures.
Abstract: In the modern applications there are lot of computing resources starting from Central Processing Units, Networks on Chips to Field Programmable Gate Arrays, each catering various types of operations. These factors motivate this research, to exploit 16-bit High Performance Variable Accuracy Reconfigurable Adder (HPVARA) and High Performance Error Tolerant Adder (HPETA-III) which are used extensively in many computing architectures for hybrid and error tolerant applications. The simulation based research outcome of the proposed HPVARA structure shows 13.69%, 15.95%, 9.82%, 22.53%, 13.56% improved Area Delay Product and 12.15%, 11.86%, 8.74%, 15.12%, 14.96% improved Power Delay Product with the computational outputs varying between 91.788% and 100% with the input operand pair compared to the existing ACA-I, ACA-II, GDA, VARA4 and conventional CSLA architectures. The second part of the research is focused on optimizing the design of the High Performance Error Tolerant Adder (HPETA-III). The proposed HPETA-III design performance is evaluated to offer a savings of logic gate count ranges from 268, 212, 173, 184, 196, 172, 68, 76, 60, 21 with respect to CSLA, VARA4, HSSSA, SAET-CSLA, ETCSLA, HSETA, HPETA-I, HPETA-II, CEETA, CEETA1 architectures respectively and also interesting results have been observed with reduced power, delay, PDP and ADP.
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TL;DR: This paper proposes logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy, and demonstrates the utility of these approximate adders in two digital signal processing architectures with specific quality constraints.
Abstract: Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. We design architectures for video and image compression algorithms using the proposed approximate arithmetic units and evaluate them to demonstrate the efficacy of our approach. We also derive simple mathematical models for error and power consumption of these approximate adders. Furthermore, we demonstrate the utility of these approximate adders in two digital signal processing architectures (discrete cosine transform and finite impulse response filter) with specific quality constraints. Simulation results indicate up to 69% power savings using the proposed approximate adders, when compared to existing implementations using accurate adders.
637 citations
29 May 2013
TL;DR: This work analysis and characterization of inherent application resilience present in a suite of 12 widely used applications from the domains of recognition, data mining, and search and proposes a systematic framework for Application Resilience Characterization (ARC), which characterizes the resilient parts using approximation models that abstract a wide range of approximate computing techniques.
Abstract: Approximate computing is an emerging design paradigm that enables highly efficient hardware and software implementations by exploiting the inherent resilience of applications to in-exactness in their computations. Previous work in this area has demonstrated the potential for significant energy and performance improvements, but largely consists of ad hoc techniques that have been applied to a small number of applications. Taking approximate computing closer to mainstream adoption requires (i) a deeper understanding of inherent application resilience across a broader range of applications (ii) tools that can quantitatively establish the inherent resilience of an application, and (iii) methods to quickly assess the potential of various approximate computing techniques for a given application. We make two key contributions in this direction. Our primary contribution is the analysis and characterization of inherent application resilience present in a suite of 12 widely used applications from the domains of recognition, data mining, and search. Based on this analysis, we present several new insights into the nature of resilience and its relationship to various key application characteristics. To facilitate our analysis, we propose a systematic framework for Application Resilience Characterization (ARC) that (a) partitions an application into resilient and sensitive parts and (b) characterizes the resilient parts using approximation models that abstract a wide range of approximate computing techniques. We believe that the key insights that we present can help shape further research in the area of approximate computing, while automatic resilience characterization frameworks such as ARC can greatly aid designers in the adoption approximate computing.
464 citations
TL;DR: It is shown that these proposed Bio-inspired Imprecise Computational blocks (BICs) can be exploited to efficiently implement a three-layer face recognition neural network and the hardware defuzzification block of a fuzzy processor.
Abstract: The conventional digital hardware computational blocks with different structures are designed to compute the precise results of the assigned calculations. The main contribution of our proposed Bio-inspired Imprecise Computational blocks (BICs) is that they are designed to provide an applicable estimation of the result instead of its precise value at a lower cost. These novel structures are more efficient in terms of area, speed, and power consumption with respect to their precise rivals. Complete descriptions of sample BIC adder and multiplier structures as well as their error behaviors and synthesis results are introduced in this paper. It is then shown that these BIC structures can be exploited to efficiently implement a three-layer face recognition neural network and the hardware defuzzification block of a fuzzy processor.
458 citations
TL;DR: This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA, and develops and compared with the regular SQRT C SLA architecture.
Abstract: Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-μm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.
377 citations
TL;DR: A novel error-tolerant adder (ETA) is proposed that is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance.
Abstract: In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain more than 65% improvement in the Power-Delay Product (PDP). One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors.
286 citations