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Journal ArticleDOI

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Abstract: This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.
Citations
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Journal ArticleDOI
TL;DR: A detailed explanation of the unique properties associated with the one-dimensional nanowire geometry will be presented, and the benefits of these properties for the various applications will be highlighted.
Abstract: Semiconductor nanowires (NWs) have been studied extensively for over two decades for their novel electronic, photonic, thermal, electrochemical and mechanical properties. This comprehensive review article summarizes major advances in the synthesis, characterization, and application of these materials in the past decade. Developments in the understanding of the fundamental principles of "bottom-up" growth mechanisms are presented, with an emphasis on rational control of the morphology, stoichiometry, and crystal structure of the materials. This is followed by a discussion of the application of nanowires in i) electronic, ii) sensor, iii) photonic, iv) thermoelectric, v) photovoltaic, vi) photoelectrochemical, vii) battery, viii) mechanical, and ix) biological applications. Throughout the discussion, a detailed explanation of the unique properties associated with the one-dimensional nanowire geometry will be presented, and the benefits of these properties for the various applications will be highlighted. The review concludes with a brief perspective on future research directions, and remaining barriers which must be overcome for the successful commercial application of these technologies.

789 citations

Journal ArticleDOI
TL;DR: In this article, the electronic transport properties of nanowire field effect transistors (NW-FETs) are discussed in detail, and four different device concepts are studied in detail.
Abstract: This paper discusses the electronic transport properties of nanowire field-effect transistors (NW-FETs). Four different device concepts are studied in detail: Schottky-barrier NW-FETs with metallic source and drain contacts, conventional-type NW-FETs with doped NW segments as source and drain electrodes, and, finally, two new concepts that enable steep turn-on characteristics, namely, NW impact ionization FETs and tunnel NW-FETs. As it turns out, NW-FETs are, to a large extent, determined by the device geometry, the dimensionality of the electronic transport, and the way of making contacts to the NW. Analytical as well as simulation results are compared with experimental data to explain the various factors impacting the electronic transport in NW-FETs.

352 citations

Journal ArticleDOI
TL;DR: In this article, the authors reviewed the recent approaches in realizing carrier-transport-enhanced CMOS, and the critical issues, fabrication techniques, and device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented.
Abstract: An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.

337 citations

Journal ArticleDOI
TL;DR: In this paper, a theoretical study of electron mobility in cylindrical gated silicon nanowires at 300 K based on the Kubo-Greenwood formula and the self-consistent solution of the Schrodinger and Poisson equations is presented.
Abstract: We present a theoretical study of electron mobility in cylindrical gated silicon nanowires at 300 K based on the Kubo-Greenwood formula and the self-consistent solution of the Schrodinger and Poisson equations. A rigorous surface roughness scattering model is derived, which takes into account the roughness-induced fluctuation of the subband wave function, of the electron charge, and of the interface polarization charge. Dielectric screening of the scattering potential is modeled within the random phase approximation, wherein a generalized dielectric function for a multi-subband quasi-one-dimensional electron gas system is derived accounting for the presence of the gate electrode and the mismatch of the dielectric constant between the semiconductor and gate insulator. A nonparabolic correction method is also presented, which is applied to the calculation of the density of states, the matrix element of the scattering potential, and the generalized Lindhard function. The Coulomb scattering due to the fixed i...

322 citations

Journal ArticleDOI
Mikael Björk1, Heinz Schmid1, Joachim Knoch1, Heike Riel1, Walter Riess1 
TL;DR: It is shown that the donor ionization energy increases with decreasing nanowire radius, and that it profoundly modifies the attainable free carrier density at values of the radius much larger than those at which quantum and dopant surface segregation effects set in.
Abstract: Electronic devices based on semiconductor nanowires will rely on the location and number of dopant atoms in the host semiconductor being controlled during the fabrication process. It has now been shown that the properties of dopant atoms — in particular, their ionization energies — change with nanowire radius more markedly than previously predicted.

308 citations

References
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Journal ArticleDOI
Yi Cui1, Zhaohui Zhong1, Deli Wang1, Wayne U. Wang1, Charles M. Lieber1 
TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Abstract: Silicon nanowires can be prepared with single-crystal structures, diameters as small as several nanometers and controllable hole and electron doping, and thus represent powerful building blocks for nanoelectronics devices such as field effect transistors. To explore the potential limits of silicon nanowire transistors, we have examined the influence of source-drain contact thermal annealing and surface passivation on key transistor properties. Thermal annealing and passivation of oxide defects using chemical modification were found to increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V‚s with peak values of 2000 nS and 1350 cm 2 /V‚s, respectively. The comparison of these results and other key parameters with state-of-the-art planar silicon devices shows substantial advantages for silicon nanowires. The uses of nanowires as building blocks for future nanoelectronics are discussed.

2,157 citations


"High-performance fully depleted sil..." refers background in this paper

  • ...High mobilities in nanowire FETs have been reported previously [10], [21], [22] and can probably be due to one or more of the following: cylindrical morphology of the channel...

    [...]

Journal ArticleDOI
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Abstract: MOSFETs with gate length down to 17 nm are reported To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed By using boron-doped Si/sub 04/Ge/sub 06/ as a gate material, the desired threshold voltage was achieved for the ultrathin body device The quasiplanar nature of this new variant of the vertical double-gate MOSFETs can be fabricated relatively easily using the conventional planar MOSFET process technologies

1,668 citations


"High-performance fully depleted sil..." refers background in this paper

  • ...Among the many innovative approaches, double-gated FinFET [3], [4], tri-gated [5], Π-gated [6], Ω-gated [7], nanowire body [8]–[11], and gateall-around (GAA) [12]–[14] MOSFETs have attracted much...

    [...]

  • ...Among the many innovative approaches, double-gated FinFET [3], [4], tri-gated [5], Π-gated [6], Ω-gated [7], nanowire body [8]–[11], and gateall-around (GAA) [12]–[14] MOSFETs have attracted much attention....

    [...]

  • ...Besides theoretical studies [15], [16], there have been several experimental attempts (although several of them suffer in gate definition) that demonstrated the advantages of GAA, or near GAA devices, e.g., relaxed body thickness yet gaining similar short-channel control as thin-body double-sided FinFET [7], [8], excellent transconductance [12], and drain-induced barrier lowering (DIBL) suppression [13]....

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  • ...1(a)]—similar to the method used in [4] for FinFET....

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Journal ArticleDOI
18 Sep 2003-Nature
TL;DR: It is shown that high-performance TFTs can be produced on various substrates, including plastics, using a low-temperature assembly process and the approach is general to a broad range of materials including high-mobility materials (such as InAs or InP).
Abstract: Thin-film transistors (TFTs) are the fundamental building blocks for the rapidly growing field of macroelectronics. The use of plastic substrates is also increasing in importance owing to their light weight, flexibility, shock resistance and low cost. Current polycrystalline-Si TFT technology is difficult to implement on plastics because of the high process temperatures required. Amorphous-Si and organic semiconductor TFTs, which can be processed at lower temperatures, but are limited by poor carrier mobility. As a result, applications that require even modest computation, control or communication functions on plastics cannot be addressed by existing TFT technology. Alternative semiconductor materials that could form TFTs with performance comparable to or better than polycrystalline or single-crystal Si, and which can be processed at low temperatures over large-area plastic substrates, should not only improve the existing technologies, but also enable new applications in flexible, wearable and disposable electronics. Here we report the fabrication of TFTs using oriented Si nanowire thin films or CdS nanoribbons as semiconducting channels. We show that high-performance TFTs can be produced on various substrates, including plastics, using a low-temperature assembly process. Our approach is general to a broad range of materials including high-mobility materials (such as InAs or InP).

1,006 citations


"High-performance fully depleted sil..." refers background or result in this paper

  • ...Considering the volume inversion in the channel [18] and to facilitate comparison with previous works [4], [7], [9]–[11],...

    [...]

  • ...Among the many innovative approaches, double-gated FinFET [3], [4], tri-gated [5], Π-gated [6], Ω-gated [7], nanowire body [8]–[11], and gateall-around (GAA) [12]–[14] MOSFETs have attracted much...

    [...]

  • ...than earlier reports on nanowire transistors [8]–[11]....

    [...]

Journal ArticleDOI
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Abstract: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion. This original method of transistor operation offers excellent device performance, in particular great increases in subthreshold slope, transconductance, and drain current. A simulation program and experiments on SIMOX structures are used to study the new device.

729 citations


"High-performance fully depleted sil..." refers result in this paper

  • ...Considering the volume inversion in the channel [18] and to facilitate comparison with previous works [4], [7], [9]–[11],...

    [...]

Journal ArticleDOI
TL;DR: The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome.
Abstract: Recently there has been tremendous progress made in the research of novel nanotechnology for future nanoelectronic applications. In particular, several emerging nanoelectronic devices such as carbon-nanotube field-effect transistors (FETs), Si nanowire FETs, and planar III-V compound semiconductor (e.g., InSb, InAs) FETs, all hold promise as potential device candidates to be integrated onto the silicon platform for enhancing circuit functionality and also for extending Moore's Law. For high-performance and low-power logic transistor applications, it is important that these research devices are frequently benchmarked against the existing Si logic transistor data in order to gauge the progress of research. In this paper, we use four key device metrics to compare these emerging nanoelectronic devices to the state-of-the-art planar and nonplanar Si logic transistors. These four metrics include: 1) CV/I or intrinsic gate delay versus physical gate length L/sub g/; 2) energy-delay product versus L/sub g/; 3) subthreshold slope versus L/sub g/; and 4) CV/I versus on-to-off-state current ratio I/sub ON//I/sub OFF/. The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome. We believe that benchmarking is a key element in accelerating the progress of nanotechnology research for logic transistor applications.

630 citations