scispace - formally typeset
Search or ask a question
Journal ArticleDOI

High Performance Lithography Hotspot Detection With Successively Refined Pattern Identifications and Machine Learning

TL;DR: This work proposes a high performance hotspot detection methodology consisting of a fast layout analyzer; 2) powerful hotspot pattern identifiers; and 3) a generic and efficient flow with successive performance refinements that achieves higher prediction accuracy for hotspots that are not previously characterized.
Abstract: Under the real and evolving manufacturing conditions, lithography hotspot detection faces many challenges. First, real hotspots become hard to identify at early design stages and hard to fix at post-layout stages. Second, false alarms must be kept low to avoid excessive and expensive post-processing hotspot removal. Third, full chip physical verification and optimization require very fast turn-around time. Last but not least, rapid technology advancement favors generic hotspot detection methodologies to avoid exhaustive pattern enumeration and excessive development/update as technology evolves. To address the above issues, we propose a high performance hotspot detection methodology consisting of: 1) a fast layout analyzer; 2) powerful hotspot pattern identifiers; and 3) a generic and efficient flow with successive performance refinements. We implement our algorithms with industry-strength engine under real manufacturing conditions and show that it significantly outperforms state-of-the-art algorithms in false alarms (2.4X to 2300X reduction) and runtime (5X to 237X reduction), meanwhile achieving similar or better hotspot accuracies. Compared with pattern matching, our method achieves higher prediction accuracy for hotspots that are not previously characterized, therefore, more detection generality when exhaustive pattern enumeration is too expensive to perform a priori. Such high performance hotspot detection is especially suitable for lithography-friendly physical design.
Citations
More filters
Journal ArticleDOI
TL;DR: This paper surveys key design for manufacturing issues for extreme scaling with emerging nanolithography technologies, including double/multiple patterning lithography, extreme ultraviolet lithographic, and electron-beam lithography.
Abstract: In this paper, we survey key design for manufacturing issues for extreme scaling with emerging nanolithography technologies, including double/multiple patterning lithography, extreme ultraviolet lithography, and electron-beam lithography. These nanolithography and nanopatterning technologies have different manufacturing processes and their unique challenges to very large scale integration (VLSI) physical design, mask synthesis, and so on. It is essential to have close VLSI design and underlying process technology co-optimization to achieve high product quality (power/performance, etc.) and yield while making future scaling cost-effective and worthwhile. Recent results and examples will be discussed to show the enablement and effectiveness of such design and process integration, including lithography model/analysis, mask synthesis, and lithography friendly physical design.

113 citations


Cites methods from "High Performance Lithography Hotspo..."

  • ...Ding et al. [46] proposed a high performance hotspot detection methodology with successive performance refinements, where both ANN and SVM are applied....

    [...]

Proceedings ArticleDOI
J. Andres Torres1
05 Nov 2012
TL;DR: This contest is aimed to provide a suite of layouts which highlight the challenges of this application: Widely different classes, limited amount of data and low prediction rates.
Abstract: With the widespread adoption of design for manufacturing techniques and design and process co-optimization as well as the increase in the complexity of the processes to manufacture integrated circuits there is pressing need in finding quickly to calibrate yet accurate and high performing methods to identify layout topologies which may cause yield loss. While full-based simulations provide the most accurate prediction possible their runtime prohibits an adoption at all levels of the design flow. Alternative traditional rule checking including pattern matching techniques are fast but have a limited application in finding locations that were not part the training set. Several approaches to improve the accuracy of the prediction to reduce the number of miss structures and false detections have been proposed, but none have yielded and acceptable tradeoff between accuracy and runtime. This contest is aimed to provide a suite of layouts which highlight the challenges of this application: Widely different classes, limited amount of data and low prediction rates.

98 citations

Journal ArticleDOI
TL;DR: A deep convolutional neural network that targets representative feature learning in lithography hotspot detection and achieves comparable or better performance on the ICCAD 2012 contest benchmark compared to state-of-the-art hotspot detectors based on deep or representative machine leaning.
Abstract: With the advancement of very large scale integrated circuits (VLSI) technology nodes, lithographic hotspots become a serious problem that affects manufacture yield. Lithography hotspot detection at the post-OPC stage is imperative to check potential circuit failures when transferring designed patterns onto silicon wafers. Although conventional lithography hotspot detection methods, such as machine learning, have gained satisfactory performance, with the extreme scaling of transistor feature size and layout patterns growing in complexity, conventional methodologies may suffer from performance degradation. For example, manual or ad hoc feature extraction in a machine learning framework may lose important information when predicting potential errors in ultra-large-scale integrated circuit masks. We present a deep convolutional neural network (CNN) that targets representative feature learning in lithography hotspot detection. We carefully analyze the impact and effectiveness of different CNN hyperparameters, through which a hotspot-detection-oriented neural network model is established. Because hotspot patterns are always in the minority in VLSI mask design, the training dataset is highly imbalanced. In this situation, a neural network is no longer reliable, because a trained model with high classification accuracy may still suffer from a high number of false negative results (missing hotspots), which is fatal in hotspot detection problems. To address the imbalance problem, we further apply hotspot upsampling and random-mirror flipping before training the network. Experimental results show that our proposed neural network model achieves comparable or better performance on the ICCAD 2012 contest benchmark compared to state-of-the-art hotspot detectors based on deep or representative machine leaning.

96 citations

Proceedings ArticleDOI
07 Nov 2016
TL;DR: A unified machine learning based hotspot detection framework, where feature extraction and optimization is guided by an information-theoretic approach and solved by a dynamic programming model, which can be naturally extended to online learning scenario.
Abstract: With the continuous shrinking of technology nodes, lithography hotspot detection and elimination in the physical verification phase is of great value. Recently machine learning and pattern matching based methods have been extensively studied to overcome runtime overhead problem of expensive full-chip lithography simulation. However, there is still much room for improvement in terms of accuracy and Overall Detection and Simulation Time (ODST). In this paper, we propose a unified machine learning based hotspot detection framework, where feature extraction and optimization is guided by an information-theoretic approach and solved by a dynamic programming model. More importantly, our framework can be naturally extended to online learning scenario, where some newly detected and verified layout patterns are integrated into the learning model. Experimental results show that the proposed batch detection model outperforms all state-of-the-art methods with 3.47% of accuracy improvement and 58.88% of ODST reduction on ICCAD-2012 contest benchmark suite. More importantly, equipped with online learning, our framework can further improve both accuracy and ODST.

90 citations

References
More filters
Proceedings ArticleDOI
28 Mar 1993
TL;DR: A learning algorithm for multilayer feedforward networks, RPROP (resilient propagation), is proposed that performs a local adaptation of the weight-updates according to the behavior of the error function to overcome the inherent disadvantages of pure gradient-descent.
Abstract: A learning algorithm for multilayer feedforward networks, RPROP (resilient propagation), is proposed. To overcome the inherent disadvantages of pure gradient-descent, RPROP performs a local adaptation of the weight-updates according to the behavior of the error function. Contrary to other adaptive techniques, the effect of the RPROP adaptation process is not blurred by the unforeseeable influence of the size of the derivative, but only dependent on the temporal behavior of its sign. This leads to an efficient and transparent adaptation process. The capabilities of RPROP are shown in comparison to other adaptive techniques. >

4,319 citations

Journal Article
TL;DR: A new technique for working set selection in SMO-type decomposition methods that uses second order information to achieve fast convergence andoretical properties such as linear convergence are established.
Abstract: Working set selection is an important step in decomposition methods for training support vector machines (SVMs). This paper develops a new technique for working set selection in SMO-type decomposition methods. It uses second order information to achieve fast convergence. Theoretical properties such as linear convergence are established. Experiments demonstrate that the proposed method is faster than existing selection methods using first order information.

1,461 citations

Proceedings ArticleDOI
13 Jun 2005
TL;DR: Guided by the EPE map, effective RET-aware detailed routing (RADAR) techniques are developed that can handle full-chip capacity to enhance the overall printability while maintaining other design closure.
Abstract: This paper attempts to reconcile the growing interdependency between nanometer lithography and physical design. We first introduce the concept of lithography hotspots and the edge placement error (EPE) map to measure the overall printability and manufacturing effort. We then adapt fast lithography simulation models to generate EPE map. Guided by the EPE map, we develop effective RET-aware detailed routing (RADAR) techniques that can handle full-chip capacity to enhance the overall printability while maintaining other design closure. RADAR is implemented in an industry strength detailed router, and tested using some 65nm designs. Our experimental results show that we can achieve up to 40% EPE reduction with reasonable CPU time.

136 citations

Proceedings ArticleDOI
18 May 2009
TL;DR: This paper presents a fast and accurate lithographic hotspot detection flow with a novel MLK (Machine Learning Kernel), based on critical feature extraction and classification, which achieves over 90% detection accuracy on average and much smaller false alarms.
Abstract: In this paper, we present a fast and accurate lithographic hotspot detection flow with a novel MLK (Machine Learning Kernel), based on critical feature extraction and classification. In our flow, layout binary image patterns are decomposed/analyzed and critical lithographic hotspot related features are defined and employed for low noise MLK supervised training. Combining novel critical feature extraction and MLK supervised training procedure, our proposed hotspot detection flow achieves over 90% detection accuracy on average and much smaller false alarms (10% of actual hotspots) compared with some previous work [9, 13], without CPU time overhead.

98 citations