High-PSR Capacitorless LDO with Adaptive Circuit for Varying Loads
30 Jan 2020-Journal of Circuits, Systems, and Computers (World Scientific Publishing Company)-Vol. 29, Iss: 11, pp 2050178
TL;DR: A capacitorless low-drop-out regulator with an NMOS pass transistor-based adaptive network to achieve high and constant power-supply rejection (PSR) for varying loads is presented.
Abstract: A capacitorless low-drop-out (LDO) regulator with an NMOS pass transistor-based adaptive network to achieve high and constant power-supply rejection (PSR) for varying loads is presented. The propos...
Citations
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TL;DR: In this article, a transient enhanced flipped voltage follower (FVF) based capless low-dropout (LDO) regulator for wide range of load currents and capacitances is presented.
7 citations
TL;DR: In this article , a low-dropout regulator (LDO) with optimized area and power is proposed for self-powered Internet of Things (IoT) applications, where a branch-based slew-rate enhancement circuit is applied without additional quiescent current.
Abstract: A fully integrated output capacitor, MOS-only reference, 55mnm low-dropout regulator (LDO) with optimized area and power is proposed in this letter for system-on-chip (SoC) in self-powered Internet of Things (IoT) applications. The small fully integrated output capacitor saves both area and cost, but brings challenges to the system’s stability and transient response. In order to improve system stability with optimized area, a dynamic attenuation buffer along with nested miller compensation are proposed to ensure sufficient phase margin over load range. To improve transient response with optimized power, a branch-based slew-rate enhancement (BBSRE) circuit is applied without additional quiescent current. Also, a multi-threshold MOS-only voltage reference is implemented to achieve sub-1V output and nanopower consumption with small area. The proposed LDO is fabricated in 55 nm CMOS process with the fully integrated capacitor of 5pF, occupying an area of 264µm×300µm. The quiescent current is 2µA with the figure-of-merit (FOM) of 2.
3 citations
TL;DR: In this article , a capacitor-less flipped voltage follower (FVF) low dropout (LDO) regulator using nested miller compensation with a large feed-forward transconductor (NMCLFT) is presented.
1 citations
TL;DR: In this paper , a capacitor-less low dropout (LDO) voltage regulator with a leading path from the power supply to the gate of the pass transistor keeps the gate-source voltage constant in the presence of supply voltage ripples that results in the PSR enhancement of the LDO.
Abstract: This paper presents a new architecture for improving power supply rejection (PSR) and load transient response in a capacitor-less low drop-out (LDO) voltage regulator. In the proposed architecture, inserting a leading path from the power supply to the gate of the pass transistor keeps the pass transistor gate-source voltage constant in the presence of the supply voltage ripples that results in the PSR enhancement of the LDO. In addition, by using a frequency compensation technique, the amount of undershoot and overshoot voltages in the presence of a sudden change of load current are reduced. Because of the creation of a zero in the LDO's transfer function, the effect of non-dominant pole on the phase of LDO is reduced, and a 58° phase margin is achieved without any off-chip capacitor. As reducing the power consumption as much as possible increases the battery life, therefore, in addition to using the current-reused technique, the transistors of control circuit are biased in the subthreshold region. The proposed regulator with a total of only 3.1 pF on-chip capacitor is designed and simulated in 180 nm complementary metal-oxide semiconductor (CMOS) technology for an output regulated voltage of 1.6 V and a load current of 50 μA to 50 mA. Post-layout simulation results show that the proposed circuit with an active area of 0.0145 mm2 and the input voltage of 1.8 to 2.4 V has only 1.504 μW power dissipation and −80 and −64 dB PSR at 1 and 10 kHz frequencies, respectively.
TL;DR: In this paper , a low dropout (LDO) circuit based on a curvature compensation benchmark and closed-loop stability is designed, which compensates for the higher order term of VBE in a BJT through the subthreshold characteristic of MOSFET and achieves the effect of curvature compensations.
Abstract: In this paper, a low dropout (LDO) circuit based on a curvature compensation benchmark and closed-loop stability is designed. This circuit compensates for the higher order term of VBE in a BJT through the subthreshold characteristic of MOSFET and achieves the effect of curvature compensation. The bandgap reference circuit provides a stable input voltage for the LDO circuit, while the source follower and adaptive bias circuit improve the response speed and closed-loop stability of the LDO circuit. The temperature drift coefficient of the bandgap circuit is 8.11 ppm/°C, the input voltage is 3–5 V, the output voltage is 2.8 V, and the linear adjustment rate is 0.22%.
References
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TL;DR: In this article, the authors proposed a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture, where the large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications.
Abstract: This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures.
484 citations
TL;DR: To the authors' knowledge, this is the first LDO that achieves such a high PSR up to 10 MHz, and Kelvin connection is also used to increase the gain-bandwidth of the LDO allowing for faster transient performance.
Abstract: A low drop-out (LDO) regulator with a feed-forward ripple cancellation (FFRC) technique is proposed in this paper. The FFRC-LDO achieves a high power-supply rejection (PSR) over a wide frequency range. Complete analysis and design steps of the FFRC-LDO are presented in this paper. Kelvin connection is also used to increase the gain-bandwidth of the LDO allowing for faster transient performance. The LDO is implemented in 0.13 ?m CMOS technology and achieves a PSR better than - 56 dB up to 10 MHz for load currents up to 25 mA. Load regulation of 1.2 mV for a 25 mA step is measured, and the whole LDO consumes a quiescent current of 50 ?A with a bandgap reference circuit included. To our knowledge, this is the first LDO that achieves such a high PSR up to 10 MHz.
234 citations
TL;DR: This paper presents design techniques for a high power supply rejection (PSR) low drop-out (LDO) regulator that is suitable for system-on-chip (SoC) applications while maintaining the capability to reduce high-frequency supply noise.
Abstract: This paper presents design techniques for a high power supply rejection (PSR) low drop-out (LDO) regulator. A bulky external capacitor is avoided to make the LDO suitable for system-on-chip (SoC) applications while maintaining the capability to reduce high-frequency supply noise. The paths of the power supply noise to the LDO output are analyzed, and a power supply noise cancellation circuit is developed. The PSR performance is improved by using a replica circuit that tracks the main supply noise under process-voltage-temperature variations and all operating conditions. The effectiveness of the PSR enhancement technique is experimentally verified with an LDO that was fabricated in a 0.18 μm CMOS technology with a power supply of 1.8 V. The active core chip area is 0.14 mm2, and the entire proposed LDO consumes 80 μA of quiescent current during operation mode and 55 μA of quiescent current in standby mode. It has a drop-out voltage of 200 mV when delivering 50 mA to the load. The measured PSR is better than -56 dB up to 4 MHz when delivering a current of 50 mA. Compared to a conventional uncompensated LDO, the proposed architecture presents a PSR improvement of 34 dB and 25 dB at 1 MHz and 4 MHz, respectively.
153 citations
TL;DR: A tri-loop LDO architecture is proposed and verified in a 65 nm CMOS process, where the output pole is set to be the dominant pole, and the internal poles are pushed to higher frequencies with only 50 μA of total quiescent current.
Abstract: A fully-integrated low-dropout regulator (LDO) with fast transient response and full spectrum power supply rejection (PSR) is proposed to provide a clean supply for noise-sensitive building blocks in wideband communication systems. With the proposed point-of-load LDO, chip-level high-frequency glitches are well attenuated, consequently the system performance is improved. A tri-loop LDO architecture is proposed and verified in a 65 nm CMOS process. In comparison to other fully-integrated designs, the output pole is set to be the dominant pole, and the internal poles are pushed to higher frequencies with only 50 μA of total quiescent current. For a 1.2 V input voltage and 1 V output voltage, the measured undershoot and overshoot is only 43 mV and 82 mV, respectively, for load transient of 0 μA to 10 mA within edge times of 200 ps. It achieves a transient response time of 1.15 ns and the figure-of-merit (FOM) of 5.74 ps. PSR is measured to be better than -12 dB over the whole spectrum (DC to 20 GHz tested). The prototype chip measures 260×90 μm
2
, including 140 pF of stacked on-chip capacitors.
148 citations
18 Jun 2007
TL;DR: This SoC LDO regulator uses 60pF of capacitance to achieve a worst-case power-supply rejection of -27dB over 50MHz and is shielded from fluctuations in the supply using an NMOS cascode that is biased using a charge pump, voltage reference, and RC filters to maintain low dropout.
Abstract: A 0.6mum 1.8V 5mA Miller-compensated SoC LDO regulator uses 60pF of capacitance to achieve a worst-case power-supply rejection of -27dB over 50MHz. The entire regulator is shielded from fluctuations in the supply using an NMOS cascode that is biased using a charge pump, voltage reference, and RC filters to maintain low dropout. The RC filter establishes a stable bias for the cascode without a significant impact on the efficiency or bandwidth of the LDO regulator.
102 citations