High-speed global on-chip interconnects and transceivers
28 Jun 2007-
TL;DR: This thesis describes methods to increase the achievable data rate of global on-chip interconnects with minimal chip area and power consumption, while maintaining data integrity.
Abstract: The data rate of global on-chip interconnects (up to 10 mm) is limited by a large distributed resistance and capacitance. This thesis describes methods to increase the achievable data rate of global on-chip interconnects with minimal chip area and power consumption, while maintaining data integrity.
The small RC bandwidth of global interconnects limits the achievable data rate. For highest bandwidth per area, all interconnect dimensions (width, spacing, height and oxide thickness) should be chosen equal and small. The bandwidth can be increased by choosing suitable termination impedances. A capacitive source impedance increases the bandwidth by a factor of three. In addition, the capacitive source impedance decreases power consumption in the interconnect. A small resistive load impedance also increases the bandwidth by a factor of three and decreases the dynamic power consumption. However, the static power consumption can still be high.
In order to maintain data integrity, a low offset sense amplifier is used to restore the low voltage swing at the output of the interconnect to full-swing. Furthermore, differential interconnects are used to be robust against supply noise, substrate noise and crosstalk from crossing interconnects. Crosstalk from neighboring interconnects that run in parallel is canceled with a single twist in every even differential interconnect and a double twist in every uneven differential interconnect. The optimal positions of the twists depend on the termination impedances.
A conventional transceiver in 0.13 μm CMOS with an inverter for both the transmitter and thereceiver, achieves 550 Mb/s/ch over a 10 mm long uninterrupted differential interconnect. Power consumption is 3.4 pJ/b at 50% data activity. An alternative transceiver in 0.13 μm CMOS, presented in this work, achieves 3 Gb/s/ch by using pulse-width pre-emphasis at the transmitter and a low-ohmic load resistance at the receiver. Power consumption is 2 pJ/b at 50% data activity. Our next improvement is a transceiver in 90m CMOS that achieves 2 Gb/s/ch by using a capacitive pre-emphasis transmitter and decision feedback equalization at the receiver. Power consumption is only 0.28 pJ/b at 50% data activity with low static power consumption.
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2,415 citations
TL;DR: This paper presents a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate.
Abstract: Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s.
83 citations
TL;DR: A set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs using an s-parameter wire-pair model and shows that a driver with series capacitance and a resistive load are fair approximations of these ideal terminations in the frequency range of interest.
Abstract: This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair model. It is shown that a driver with series capacitance on the one hand and a resistive load on the other, are fair approximations of these ideal terminations in the frequency range of interest. From a perspective of power efficiency, a capacitive driver is preferred, as the series capacitance reduces the voltage swing along the line which reduces dynamic power consumption. To reduce cross-talk and maintain data integrity, parallel differential interconnects with alternatingly one or two twists are used. In combination with a low offset dynamic sense amplifier at the receiver, and a low-power decision feedback equalization technique with analog feedback, gigabit communication is demonstrated at very low power consumption. A point-to-point link on a 90 nm CMOS test chip achieves 2 Gb/s over 10 mm long interconnects, while consuming 0.28 pJ/bit corresponding to 28 fJ/bit/mm, which is much lower than competing designs.
82 citations
Cites background or methods from "High-speed global on-chip interconn..."
...32 m between neighboring interconnects, and derived k mm and pF/mm from measurements [17]....
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...With this s-parameter model, the transfer function from to can readily be calculated [17]:...
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...7 mm ( , and being the wire resistance, inductance and capacitance per unit length) [17]....
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Proceedings Article•
01 Jan 2006
TL;DR: In this article, a bus-transceiver test chip in a 0.13-μm, 1.2-V, 6-M copper CMOS process has been designed using 10mm-long differential interconnects with wire widths and spacing of only 0.4 μm.
Abstract: Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. Repeaters can partly bridge this gap, but the classical repeater insertion approach requires a large number of repeaters while the intrinsic data capacity of each interconnect-segment is only partially used. In this paper we analyze interconnects and show how a combination of layout, termination and equalization techniques can significantly increase the data rate for a given length of uninterrupted interconnect. To validate these techniques, a bus-transceiver test chip in a 0.13-μm, 1.2-V, 6-M copper CMOS process has been designed. The chip uses 10-mm-long differential interconnects with wire widths and spacing of only 0.4 μm. Differential interconnects are insensitive to common-mode disturbances (e.g., non-neighbor crosstalk) and enable the use of twists to mitigate neighbor-to-neighbor crosstalk. With transceivers operating in conventional mode, the chip achieves only 0.55 Gb/s/ch. The achievable data rate increases to 3 Gb/s/ch (consuming 2 pJ/bit) with a pulse-width pre-emphasis technique, used in combination with resistive termination.
81 citations
Book•
01 Dec 2011
TL;DR: This paper presents a comparison of the designed Semi-Serial Interconnects and Circuit Techniques for PVT Variation Tolerance and their applications in On-Chip Communication and Interconnect Design Techniques.
Abstract: Introduction.- On-Chip Communication.- Interconnect Design Techniques.- Design of Delay-Insensitive Current Sensing Interconnects.- Enhancing Completion Detection Performance.- Energy Efficient Semi-Serial Interconnect.- Comparison of the Designed Interconnects.- Circuit Techniques for PVT Variation Tolerance.
10 citations
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TL;DR: Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays, which is good news since these "local" wires dominate chip wiring.
Abstract: Concern about the performance of wires wires in scaled technologies has led to research exploring other communication methods. This paper examines wire and gate delays as technologies migrate from 0.18-/spl mu/m to 0.035-/spl mu/m feature sizes to better understand the magnitude of the the wiring problem. Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays. This result is good news since these "local" wires dominate chip wiring. Despite this scaling of local wire performance, computer-aided design (CAD) tools must still become move sophisticated in dealing with these wires. Under scaling, the total number of wires grows exponentially, so CAD tools will need to handle an ever-growing percentage of all the wires in order to keep designer workloads constant. Global wires present a more serious problem to designers. These are wires that do not scale in length since they communicate signals across the chip. The delay of these wives will remain constant if repeaters are used meaning that relative to gate delays, their delays scale upwards. These increased delays for global communication will drive architectures toward modular designs with explicit global latency mechanisms.
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28 Jun 1998TL;DR: The techniques described in this book, which were once used only in supercomputers, are now essential to the correct and efficient operation of any type of digital system.
Abstract: What makes some computers slow? What makes some digital systems operate reliably for years while others fail mysteriously every few hours? Why do some systems dissipate kilowatts while others operate off batteries? These questions of speed, reliability, and power are all determined by the system-level electrical design of a digital system. Digital Systems Engineering presents a comprehensive treatment of these topics. It combines a rigorous development of the fundamental principles in each area with down-to-earth examples of circuits and methods that work in practice. The book not only can serve as an undergraduate textbook, filling the gap between circuit design and logic design, but also can help practicing digital designers keep up with the speed and power of modern integrated circuits. The techniques described in this book, which were once used only in supercomputers, are now essential to the correct and efficient operation of any type of digital system.
672 citations