Patent•
High voltage semiconductor device
04 Dec 1984-
TL;DR: In this article, a depletion layer formed throughout a portion in at least a high voltage mode of operation of the device, such as, by reverse biasing a rectifying junction, was introduced.
Abstract: A field effect transistor, a bipolar transistor, a PIN diode, a Schottky rectifier or other high voltage semiconductor device comprise a semiconductor body having a depletion layer formed throughout a portion in at least a high voltage mode of operation of the device, such as, by reverse biasing a rectifying junction. The known use of a single high-resistivity body portion of one conductivity type to carry both the high voltage and to conduct current results in a series resistivity increasing approximately in proportion with the square of the breakdown voltage. This square-law relationship is avoided by the present invention in which a depleted body portion comprising an interleaved structure of first and second regions of alternating conductivity types carries the high voltage which occurs across the depleted body portion. The thickness and doping concentration of each of these first and second regions are such that when depleted the space charge per unit area formed in each of these regions is balanced at least to the extent that an electric field resulting from any imbalance is less than the critical field strength at which avalanche breakdown would occur in the body portion. The first regions in at least one mode of operation of the device provide electrically parallel current paths extending through the body portion.
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Patent•
01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
1,501Â citations
Patent•
31 May 2006TL;DR: In this article, a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance.
Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.
664Â citations
Patent•
17 Sep 1991TL;DR: In this article, the CB-layer was introduced, where two kinds of semiconductor regions with opposite types of conduction are alternatively arranged, viewed from any cross-section parallel to the interface between the layer itself and the n + (or p + )-region.
Abstract: A semiconductor power device wherein the reverse voltage across the p + -regions(s) and the n + -regions(s) is sustained by a composite buffer layer, shortly as CB-layer. The CB-layer contains two kinds of semiconductor regions with opposite types of conduction. These two kinds of regions are alternatively arranged, viewed from any cross-section parallel to the interface between the layer itself and the n + (or p + )-region. Whereas the hitherto-used voltage sustaining layer contains only one kind of semiconductor with single type of conduction in the same sectional view. Design guidelines are also provided in this invention. The relation between the on-resistance in unit area Ron and the breakdown voltage V B of the CB-layer invented is Ron ocV B 113 which represents a breakthrough to the conventional voltage sustaining layer, whereas the other performances of the power devices remain almost unchanged.
517Â citations
Patent•
29 Jun 2007
TL;DR: In this article, the authors proposed a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost.
Abstract: An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film
323Â citations
Patent•
16 Jul 1999
TL;DR: In this paper, a super-junction semiconductor device with a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state is described.
Abstract: This invention clarifies the effects of parameters and enables the mass production of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. The quantity of impurities in n drift regions is within the range between 100% and 150% or between 110% and 150% of the quantity of impurities in p partition regions. The impurity density of either one of the n drift regions and the p partition regions is within the range between 92% and 108% of the impurity density of the other regions. In addition, the width of either one of the n drift regions and the p partition regions is within the range between 94% and 106% of the width of the other regions.
286Â citations
References
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Patent•
28 Jul 1977
TL;DR: In this paper, a logic element employing fixed threshold and variable threshold transistors electrically connected together in a unique manner to form a latch can be made to retain data by keeping certain internal nodes at a high or low voltage level.
Abstract: There is described a logic element employing fixed threshold and variable threshold transistors electrically connected together in a unique manner to form a latch. The latch can be made to retain data by keeping certain internal nodes at a high or low voltage level. As such it acts as an ordinary semiconductor memory latch, whose data can be changed by externally overriding the internal voltage levels of the latch cell. The novel results of the cell described are achieved by replacing one or several of the transistors in the latch by specially constructed transistors, whose threshold voltage can be raised or lowered upon application of a relatively high voltage pulse between their gate and substrate. By application of such a high voltage pulse, the data stored in the latch can be translated into controlled threshold shifts of the variable threshold transistors, which uniquely represent the initial latch state. Therefore, if power is removed and then returned, the latch will always settle into a state dictated by the final state that existed in the latch before the high voltage pulse was applied. In this way the variable threshold elements of the latch cell make it a non-volatile memory element. It can be used either as a read/write memory, using its latch property, or as a read-only memory, using the variable threshold transistors to cause it to always latch in a predetermined manner.
115Â citations
Patent•
13 Apr 1979TL;DR: In this paper, a multilayered GaAs structure is proposed to enhance the mobility of GaAs using molecular beam epitaxy (MBE) to enhance GaAs mobility.
Abstract: The mobility of a relatively narrow bandgap semiconductor material can be significantly enhanced by incorporating it into a multilayered structure (10) comprising a first plurality of layers (12) of a relatively narrow bandgap form of the material and a second plurality of wider bandgap semiconductor layers (14) interleaved with and contiguous with the first plurality. The wide bandgap and narrow bandgap layers are substantially lattice-matched to one another, and the wide bandgap layers are doped such that its product of impurity concentration and thickness is greater than the same product in the narrow bandgap layers. The fabrication of the structure by molecular beam epitaxy (MBE) to enhance the mobility of GaAs is specifically described. In this case, the narrow bandgap layers (12) comprise GaAs and are unintentionally doped to about 1014/cm3, whereas the wide bandgap layers (14) comprise AlGaAs doped n-type to about 1016 to 1018/cm3. The incorporation of this structure in an FET is also described.
77Â citations
Patent•
21 Jul 1977TL;DR: In this article, an improved high voltage Schottky barrier diode is proposed, which includes a semiconductor layer having two adjacent sublayers of the same type conductivity but different doping concentrations.
Abstract: An improved high voltage Schottky barrier diode includes a semiconductor layer having two adjacent sublayers of the same type conductivity but different doping concentrations. A plurality of isolated discrete regions of a second type conductivity opposite to that of the first are provided along the boundary region between the sublayers and beneath the Schottky junction. The invention results in an improved high voltage Schottky diode in which the reverse characteristics are substantially enhanced.
41Â citations
Patent•
09 Aug 1978TL;DR: In this paper, a vertical insulated gate field effect transistor is fabricated by masking the three semiconductor layers and etching the third layer and part of the second layer to form a groove, diffusing second conductivity impurities to a shallow depth in the groove, continue the etching to extend the groove through the second layers into the first layer.
Abstract: A vertical insulated gate field effect transistor having a first first conductivity layer, a second second conductivity layer thereon, a third first conductivity layer thereon, a groove extending from the surface of the third layer through the second layer into the first layer, a layer of insulation and gate material in the groove and a shallow first conductivity vertical region extending from the third layer into the second layer along the groove to form a short channel in the second layer with a shallow device junction. The device is fabricated by masking the three semiconductor layers and etching the third layer and part of the second layer to form a groove, diffusing second conductivity impurities to a shallow depth in the groove, continue the etching to extend the groove through the second layer into the first layer. A layer of insulation and gate material are formed in the groove to produce the vertical channel.
36Â citations
Patent•
17 Feb 1978
TL;DR: In this article, a V-groove metal oxide semiconductor field effect transistor (V-MOSFET) is described, where a gate electrode is formed over an insulating layer in the V-Groove, a source electrode connects to said source and channel regions, and a drain electrode is connected to said drain region.
Abstract: A V-groove metal oxide semiconductor field effect transistor (V-MOSFET) including a body of semiconductor material having three plane regions defining two plane rectifying junctions. A V-groove extends into said body through said two junctions from one surface. The plane region at said surface comprises the source, the intermediate plane region, the channel, and the other region, the drain. A gate electrode is formed over an insulating layer in said groove, a source electrode connects to said source and channel regions and a drain electrode is connected to said drain region. A moat surrounds said transistor and penetrates the source and channel regions and a field electrode is disposed over an insulating layer covering the moat wall.
34Â citations