Patent•
High-voltage vertical power component
23 May 2013-
TL;DR: In this article, a vertical power component including a silicon substrate of a first conductivity type, a lower surface of the substrate supporting a single electrode, and an upper region of the second conductivity Type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.
Abstract: A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.
Citations
More filters
Patent•
17 Jun 2013
TL;DR: In this paper, an integrated circuit device including a through-silicon-via (TSV) structure and methods of manufacturing the same are provided, which may include the TSV structure penetrating through a semiconductor structure.
Abstract: An integrated circuit device including a through-silicon-via (TSV) structure and methods of manufacturing the same are provided. The integrated circuit device may include the TSV structure penetrating through a semiconductor structure. The TSV structure may include a first through electrode unit including impurities of a first concentration and a second through electrode unit including impurities of a second concentration greater than the first concentration.
14 citations
Patent•
07 Feb 2013TL;DR: In this article, a highvoltage vertical power component including a silicon substrate of a first conductivity type and a first semiconductor layer of the second conductivity types extending into the silicon substrate from an upper surface of the substrate, where the component periphery includes: a porous silicon ring extending into a substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the first conductivities type, extending from a lower surface of a silicon surface to the polysilicon ring.
Abstract: A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring.
5 citations
Patent•
17 Jun 2013TL;DR: In this paper, an integrated circuit device including a through-silicon-via (TSV) structure and methods of manufacturing the same are provided, which may include the TSV structure penetrating through a semiconductor structure.
Abstract: An integrated circuit device including a through-silicon-via (TSV) structure and methods of manufacturing the same are provided. The integrated circuit device may include the TSV structure penetrating through a semiconductor structure. The TSV structure may include a first through electrode unit including impurities of a first concentration and a second through electrode unit including impurities of a second concentration greater than the first concentration.
2 citations
Patent•
10 Nov 2015TL;DR: In this article, the authors describe a bi-directional power switch having first (TFA) and second (TH) connected thyristors in anti-parallel between the first (A1) and the second (A2) of the switch conduction terminals.
Abstract: L'invention concerne un commutateur bidirectionnel de puissance comportant des premier (AGT) et second (TH) thyristors connectes en antiparallele entre des premiere (A1) et deuxieme (A2) bornes de conduction du commutateur, le premier thyristor (AGT) etant un thyristor a gâchette d'anode, le second thyristor (TH) etant un thyristor a gâchette de cathode, et les gâchettes (G AGT , G TH ) des premier (AGT) et second (TH) thyristors etant reliees a une meme borne de commande (G) du commutateur, dans lequel au moins une diode (C1, C2) ou au moins une resistance (C1, C2) separe la gâchette (G AGT ) du premier thyristor (AGT) de la gâchette (G TH ) du second thyristor (TH). The invention relates to a bi-directional power switch having first (TFA) and second (TH) connected thyristors in anti-parallel between the first (A1) and second (A2) of the switch conduction terminals, the first thyristor (TMA) being a thyristor anode gate, the second thyristor (TH) being a thyristor cathode gate and the gates (G AGT G TH) first (AGT) and second (TH) thyristors being connected to a common control terminal ( G) of the switch, wherein at least one diode (C1, C2) or at least one resistor (C1, C2) between the gate (G AGT) of the first thyristor (AGT) to the gate (G TH) of the second thyristor ( TH).
2 citations
Patent•
04 Mar 2020
TL;DR: In this paper, a power switching device may include a semiconductor substrate and a body region comprising an n-type dopant, the body region disposed in an inner portion of the semiconducting substrate; a first base layer disposed adjacent a first surface of the substrate, the first p-base layer comprising a p-type op-drug, the second base layer comprising p-drone, and a second field stop layer arranged between the first base and the body regions.
Abstract: A power switching device may include a semiconductor substrate and a body region comprising an n-type dopant, the body region disposed in an inner portion of the semiconductor substrate; a first base layer disposed adjacent a first surface of the semiconductor substrate, the first p-base layer comprising a p-type dopant; a second base layer disposed adjacent a second surface of the semiconductor substrate, the second base layer comprising a p-type dopant; a first emitter region, disposed adjacent the first surface of the semiconductor substrate, the first emitter region comprising a n-type dopant; a second emitter-region, disposed adjacent the second surface of the semiconductor substrate, the second emitter-region comprising a n-type dopant; a first field stop layer arranged between the first base layer and the body region, the first field stop layer comprising a n-type dopant; and a second field stop layer arranged between the second base layer and the body region, the second field stop layer comprising a n-type dopant.
1 citations
References
More filters
Patent•
09 May 1997TL;DR: In this paper, a device with at least one noise-sensitive element, one noise generating element, and a porous silicon barrier in the substrate is described, which isolates the noise sensitive element from the signals coupled into the substrate by the noise generator.
Abstract: A device with at least one noise-sensitive element, at least one noise-generating element, and a porous silicon barrier in the substrate is disclosed. The porous silicon barrier isolates the noise-sensitive element from the signals coupled into the substrate by the noise-generating element. A process for making this device is also disclosed.
41 citations
Patent•
IBM1
TL;DR: In this article, a latch-up robust p-n diode is configured for an integrated circuit with a substrate of a first polarity, a trench structure in the substrate, and a well region of a second polarity abutting the trench structure.
Abstract: A method and structure for an integrated circuit comprising a substrate of a first polarity; a trench structure in the substrate; a well region of a second polarity abutting the trench structure; and a heavily doped region of the second polarity abutting the trench structure, wherein the heavily doped region is adapted to suppress latch-up in the integrated circuit, wherein the heavily doped region comprises a sub-collector region, and wherein the trench structure comprises a deep trench structure or a trench isolation structure. The integrated circuit further comprises a p+ anode in the well region and a n+ cathode in the well region, wherein the integrated circuit is configured as a latchup robust p-n diode. In another embodiment, the integrated circuit further comprises a p+ anode in the well region; a n+ cathode in the well region; and a gate structure over the p+ anode and n+ cathode.
32 citations
Patent•
12 May 2006
TL;DR: In this article, a multiple-cell insulated-gate-bipolar-transistor (IGBT) chip is disclosed which includes a semiconductor substrate having formed therein a p + -type collector region and an n − -type base region, with a pn junction therebetween.
Abstract: A multiple-cell insulated-gate-bipolar-transistor chip is disclosed which includes a semiconductor substrate having formed therein a p + -type collector region and an n − -type base region, with a pn junction therebetween. An annular trench is etched in the substrate so as to surround the array of IGBT cells. Received in the trench are a dielectric layer which is held against the base region, and an electroconductive layer which is held against the base region via the dielectric layer and which is electrically coupled to the collector region. When the pn junction between the collector and base regions is reverse biased, the electroconductive layer creates at the annular periphery of the base region a depletion layer which is joined to a depletion layer created in the base region by the pn junction, thereby preventing current leakage from the side surfaces of the IGBT chip.
28 citations
Patent•
04 Sep 2003TL;DR: In this article, a hollow region is formed in a silicon substrate by a plurality of openings formed in the silicon layer on the hollow region, which are filled with a buried film.
Abstract: A hollow region is formed in a silicon substrate. A plurality of openings formed in the silicon layer on the hollow region is filled with a buried film. The bottom portion of the hollow region is formed with a plurality of silicon pillars, which support the silicon layer.
25 citations
Patent•
30 Jan 2003
TL;DR: In this paper, an ion diffusion region with the first type conductivity is formed in the epitaxial layer and surrounds the sidewall and bottom of the deep trench, and an undoped polysilicon layer fills the deep trenches.
Abstract: A deep trench isolation structure of a high-voltage device and a method of forming thereof. An epitaxial layer with a second type conductivity is formed on a semiconductor silicon substrate with a first type conductivity. A deep trench passes through the epitaxial layer. An ion diffusion region with the first type conductivity is formed in the epitaxial layer and surrounds the sidewall and bottom of the deep trench. An undoped polysilicon layer fills the deep trench.
18 citations