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Highly Linear Mixer for On-chip RF Test in 130 nm CMOS

01 Jan 2007-

AbstractThe complexity of wireless communication integrated circuits is increasing day by day due to the trend of multifunction and multistandard support. This has not only increased the production cost of ...

Topics: Integrated circuit (55%), CMOS (54%)

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Citations
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01 Apr 1983

377 citations


Book ChapterDOI
01 Jan 2003
Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

207 citations


Proceedings ArticleDOI
22 Jun 2008
TL;DR: It is shown that as CMOS process technology evolves, the double-balanced passive mixer architecture will become more favorable and yield improved performance.
Abstract: In this paper, fundamental performance limits and scaling of a double-balanced passive mixer are examined. Analysis of the passive double-balanced mixer will show how its performance metrics are directly affected by the down-scaling of the transistor gate length, LG. We analyze the performance in terms of conversion gain (GC), 1-dB compression point (P1-dB) which we derive, and SSB Noise Figure (NF). We will show that as CMOS process technology evolves, the double-balanced passive mixer architecture will become more favorable and yield improved performance. This is verified through simulation and modeling results for mixers designed in CMOS 350 nm to 32 nm technology. We introduce a mixerpsilas figure-of-merit (FOMMIXER) to compare performance with technology scaling. Circuit designers and system architects can use this paper to find a suitable process technology that will meet their specifications.

22 citations


DOI
01 Jan 2011
TL;DR: This research work analyzes and realizes a new approach of replacing this analog front-end in the transmitter by digital signal processing that upsamples, combines and upconverts the carriers, followed by a single DAC that generates the RF signal without further upconversion.
Abstract: Traditionally the front-end of a transmitter for cable television designed for the DOCSIS standard consists of a combination of multiple DACs and analog mixers. In this traditional transmitter architecture, in each front-end a single carrier is converted in a DAC and upconverted to the desired RF frequency. This research work analyzes and realizes a new approach of replacing this analog front-end in the transmitter by digital signal processing that upsamples, combines and upconverts the carriers, followed by a single DAC that generates the RF signal without further upconversion. The new approach has the advantage that the complexity of a multi-carrier transmitter is reduced, because less analog components are required which require tuning and calibration. Chapter 2 presents the communication system and the challenges when many channels are combined. A theoretical study about the consequences of the combining of multiple channels in the digital domain on the properties of the signal that is converted with the DAC is given and the optimal level for amplitude clipping in the case of a limited number of carriers and in the case of many carriers is analyzed. Chapter 3 introduces the DOCSIS broadcast system and the RF requirements that are specified in the standard. From this standard the requirements on a single transmitter that is capable to transmit multiple channels is derived. Chapter 4 studies the traditional DAC/mixer combination and the requirements for the individual components that are needed and from these specifications the power consumption of such a transmitter is estimated and is used to compare against the proposed method. Using such an architecture the minimum power consumption is estimated to be about 1.2W per channel that is being broadcasted. In Chapter 5 the advantages of increasing the digitization and of advanced CMOS technologies are explained. The new approach of combining the carriers in the digital signal processing is analyzed and requirements for the digital signal processing functions are set. The number of carriers that can be transmitted using a single ’all-digital’ transmitter increases significantly, compared to the traditional analog dual conversion transmitter, because the complexity of the analog core of the ’all-digital’ transmitter is independent of the number of channels. The ’all-digital’ transmitter can broadcast all channels that could be present in the full DOCSIS band with a single DAC. The main limitation in the number of channels is the limit in power dissipation that can be handled by the package, since adding more channels does only affect the digital signal processing and does not increase the complexity in the analog domain. Chapter 6 proposes the implemented ’all-digital’ transmitter architecture. Of this architecture the requirements for the building blocks are studied and the power consumption of these digital circuits is estimated. In Chapter 7 the digital-to-analog converter used in this ’All-digital’ transmitter is analyzed and several models are derived to estimate the performance of the DAC in case of imperfections. A new framework is given for modeling and analysis of current steering DAC performance in the case of broadband signals, and especially at high sample rates. For such broadband signals, error mechanisms that create distortion around the mid-scale transitions are more dominant in the performance of the system than error mechanisms that create distortion at the extremes of the amplitude range. Using fully binary DACs or DACs with a low segmentation results in a higher distortion for signals that have wideband properties than for narrowband signals. When the DAC performance is affected by output conductance, a higher output conductance is allowed to achieve a similar performance for wideband signals than for a narrowband signal. Using these models an architecture for the DAC is selected and the measurement results of the realized DAC are shown. In Chapter 8 the IC implementations are being discussed. The transmitter concepts have been used in a rationalized manner to design and implement a 12-bit 2.8GS/s DAC in combination with digital signal processing that upsamples, combines and upconverts the carriers in a 90nm CMOS process, which serves as a vehicle IC to verify the validity of the ’all-digital’ transmitter concepts proposed in this thesis. Based on this DAC, three different versions of a complete ’all-digital’ transmitter, which consist of a combination of the digital signal processing and a DAC, were designed and implemented as ICs. The first two versions, the second being a redesigned version of the first one, use current mode logic for the digital signal processing, which is optimized to be able to run at the desired sample frequency of 2.8GS/s. Since the digital signal processing is made in current mode logic and synchronous with the DAC clock, no interference is observed. The third version uses static CMOS logic in combination with several methods, such as the use of poly-clock phases, to reduce the interference from the digital signal processing to the sensitive analog circuits. It is shown that the combination of these techniques to reduce the interference is sufficient to achieve the required performance. The preferred logic style to implement the digital circuits is standard CMOS logic, which is efficient in terms of power consumption and effort to implement the digital circuits. The proposed multi-carrier transmitter architecture is compared against the traditional multi-carrier transmitter. It has been shown that the proposed multi-carrier DOCSIS transmitter can be more power and area efficient when multiple channels are being broadcasted than multiple traditional DOCSIS transmitters that have their outputs combined. In the case of 64 channels the expected reduction in the power consumption is more than 90%.

8 citations


Cites background from "Highly Linear Mixer for On-chip RF ..."

  • ...Conversion loss The theoretical conversion loss of an ideal passive mixer without the switch resistance is equal to [61]...

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01 Jan 2016
Abstract: In this thesis work, a highly linear passive attenuator and mixer were designed to be used in a wide-band Transmission Observation Receiver (TOR). The TOR is a low IF receiver that accepts RF frequencies from 2GHz to 7GHz, and produces corresponding IF bandwidths of 280MHz to 990MHz respectively, using low side LO injection. The dynamic range is maximized by using passive topologies for both the attenuator and the mixer. The system is dealing with different power levels ranging from -30dBm to +1dBm, and hence, a programmable digital step attenuator is used to attenuate large signals. It provides a maximum of 31dB of attenuation in 1dB steps. Different mixer architectures were compared, including CMOS mixer, mixer with dummy switches and quadrature mixer. Also, the performance of the mixer in both voltage mode and current mode was investigated. A double balanced passive mixer in voltage mode, with dummy switches was adopted in the final system since it proved to be the best in terms of meeting the requirements. The work was carried out in Ericsson in Lund, using Cadence, 65nm process. The circuit is true differential and it uses a supply voltage of 1.2V. The final results show a spurious free dynamic range of higher than 85dBc, minimum in band IIP3 of +15dBm , maximum IIP3 of +50dBm and a worst input return loss of less than -10dB. The amplitude and phase precision over the observation bandwidth were quite good, a worst phase error of less than 3 degrees was recorded and an amplitude error of 0.5dB. (Less)

3 citations


Cites background from "Highly Linear Mixer for On-chip RF ..."

  • ...Conversion gain of this mixer is independent of the bias current [10]....

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  • ...One of the disadvantage in such mixers is the need of large LO drive signal to turn the MOS switches on/off [10]....

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  • ...The drain-source of passive mixers transistors are slightly biased with positive VDS for optimum conversion loss and optimized IMD performance [10]....

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References
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Journal Article
TL;DR: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Abstract: 53 ■ IEEE CIRCUITS & DEVICES MAGAZINE ■ NOVEMBER/DECEMBER 2005 THE DESIGN OF CMOS RADIOFREQUENCY INTEGRATED CIRCUITS, 2ND ED By Thomas Lee, Cambridge University Press, 2003. All-CMOS radio transceivers and system-on-a-chip are rapidly making inroads into a wireless market that, for years, was dominated by bipolar solutions. On wireless LAN and Bluethooth, RF CMOS is especially dominant, and it is becoming also in GSM cellular and GPS receivers. Hence, books that cover this widespread domain respond to a real need. The first edition of this book, published on 1998, was a pioneering textbook on the field of RF CMOS design. This second edition is a very interesting and upgraded version that includes new material and revised topics. In particular, it now includes a chapter on the fundamentals of wireless systems. The chapter on IC components is greatly expanded and now follows that on passive RLC components. The chapter on MOS devices has been updated since it includes the understanding of the model for the shorth-channel MOS and considers and discusses the scaling trends and its impact on the next several years. It has also expanded the topic of power amplifiers; indeed, it now also covers techniques for linearization and efficiency enhancement. Low-noise amplifiers, oscillators, and phase noise are now expanded and treated with more detail. Moreover, the chapter on transceiver architectures now includes much more detail, especially on direct-conversion architecture. Finally, additional commentary on practical details on simulations, floorplanning, and packaging has been added. The first edition of this book widely covered all the main arguments needed in the CMOS design context and provided a bridge between system and circuit issues. This second edition, which is upgraded and improved, is really useful, both in the industry and academia, for the new generation of RF engineers. Indeed, it is suited for students taking courses on RF design and is a valuable reference for practicing engineers. Of course, the arguments treated in the textbook lead up to low-frequency analog design IC topics. Hence, readers have to be intimately familiar with that subject. The book is divided into 20 chapters: 1) A Nonlinear History of Radio 2) Overview of Wireless Principles 3) Passive RLC Networks 4) Characteristics of Passive IC Components 5) A Review of MOS Device Physics; 6) Distributed Systems 7) The Smith Chart and S-Parameters 8) Bandwidth Estimation Techniques 9) High-Frequency Amplifier Design 10) Voltage References and Biasing 11) Noise 12) LNA Design 13) Mixers 14) Feedback Amplifiers 15) RF Power Amplifiers 16) Phase Locked Loop 17) Oscillators and Synthesizers 18) Phase Noise 19) Architectures 20) RF Circuits Through the Ages. Moreover, it contains over 100 circuit diagrams and many homework problems. Gaetano Palumbo

3,897 citations


Book
05 Jun 2012
Abstract: This book, first published in 2004, is an expanded and thoroughly revised edition of Tom Lee's acclaimed guide to the design of gigahertz RF integrated circuits. A new chapter on the principles of wireless systems provides a bridge between system and circuit issues. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded. The chapter on architectures now contains several examples of complete chip designs, including a GPS receiver and a wireless LAN transceiver, that bring together the theoretical and practical elements involved in producing a prototype chip. Every section has been revised and updated with findings in the field and the book is packed with physical insights and design tips, and includes a historical overview that sets the whole field in context. With hundreds of circuit diagrams and homework problems this is an ideal textbook for students taking courses on RF design and a valuable reference for practising engineers.

2,875 citations


Book
01 Nov 1997

2,454 citations


"Highly Linear Mixer for On-chip RF ..." refers background in this paper

  • ...34 Thus, it is apparent that a stronger interferer with a frequency, which is close to the actual signal frequency, will corrupt the signal due to 3 order intermodulation products because the fundamental increases in proportion to A, whereas IM3 increases in proportion to A [20]....

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  • ...Odd order harmonics make the system nonlinear [20]....

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Book
01 Jan 1982

1,413 citations


Journal ArticleDOI
Abstract: Flicker noise in the mixer of a zero- or low-intermediate frequency (IF) wireless receiver can compromise overall receiver sensitivity. A qualitative physical model has been developed to explain the mechanisms responsible for flicker noise in mixers. The model simply explains how frequency translations take place within a mixer. Although developed to explain flicker noise, the model predicts white noise as well. Simple equations are derived to estimate the flicker and white noise at the output of a switching active mixer. Measurements and simulations validate the accuracy of the predictions, and the dependence of mixer noise on local oscillator (LO) amplitude and other circuit parameters.

651 citations