Highly Linear Mixer for On-chip RF Test in 130 nm CMOS
01 Jan 2007-
TL;DR: The complexity of wireless communication integrated circuits is increasing day by day due to the trend of multifunction and multistandard support as mentioned in this paper. This has not only increased the production cost of...
Abstract: The complexity of wireless communication integrated circuits is increasing day by day due to the trend of multifunction and multistandard support. This has not only increased the production cost of ...
Citations
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01 Jan 2003
TL;DR: In this paper, an expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0
207 citations
22 Jun 2008
TL;DR: It is shown that as CMOS process technology evolves, the double-balanced passive mixer architecture will become more favorable and yield improved performance.
Abstract: In this paper, fundamental performance limits and scaling of a double-balanced passive mixer are examined. Analysis of the passive double-balanced mixer will show how its performance metrics are directly affected by the down-scaling of the transistor gate length, LG. We analyze the performance in terms of conversion gain (GC), 1-dB compression point (P1-dB) which we derive, and SSB Noise Figure (NF). We will show that as CMOS process technology evolves, the double-balanced passive mixer architecture will become more favorable and yield improved performance. This is verified through simulation and modeling results for mixers designed in CMOS 350 nm to 32 nm technology. We introduce a mixerpsilas figure-of-merit (FOMMIXER) to compare performance with technology scaling. Circuit designers and system architects can use this paper to find a suitable process technology that will meet their specifications.
24 citations
DOI•
01 Jan 2011
TL;DR: This research work analyzes and realizes a new approach of replacing this analog front-end in the transmitter by digital signal processing that upsamples, combines and upconverts the carriers, followed by a single DAC that generates the RF signal without further upconversion.
Abstract: Traditionally the front-end of a transmitter for cable television designed for the DOCSIS standard consists of a combination of multiple DACs and analog mixers. In this traditional transmitter architecture, in each front-end a single carrier is converted in a DAC and upconverted to the desired RF frequency. This research work analyzes and realizes a new approach of replacing this analog front-end in the transmitter by digital signal processing that upsamples, combines and upconverts the carriers, followed by a single DAC that generates the RF signal without further upconversion. The new approach has the advantage that the complexity of a multi-carrier transmitter is reduced, because less analog components are required which require tuning and calibration. Chapter 2 presents the communication system and the challenges when many channels are combined. A theoretical study about the consequences of the combining of multiple channels in the digital domain on the properties of the signal that is converted with the DAC is given and the optimal level for amplitude clipping in the case of a limited number of carriers and in the case of many carriers is analyzed. Chapter 3 introduces the DOCSIS broadcast system and the RF requirements that are specified in the standard. From this standard the requirements on a single transmitter that is capable to transmit multiple channels is derived. Chapter 4 studies the traditional DAC/mixer combination and the requirements for the individual components that are needed and from these specifications the power consumption of such a transmitter is estimated and is used to compare against the proposed method. Using such an architecture the minimum power consumption is estimated to be about 1.2W per channel that is being broadcasted. In Chapter 5 the advantages of increasing the digitization and of advanced CMOS technologies are explained. The new approach of combining the carriers in the digital signal processing is analyzed and requirements for the digital signal processing functions are set. The number of carriers that can be transmitted using a single ’all-digital’ transmitter increases significantly, compared to the traditional analog dual conversion transmitter, because the complexity of the analog core of the ’all-digital’ transmitter is independent of the number of channels. The ’all-digital’ transmitter can broadcast all channels that could be present in the full DOCSIS band with a single DAC. The main limitation in the number of channels is the limit in power dissipation that can be handled by the package, since adding more channels does only affect the digital signal processing and does not increase the complexity in the analog domain. Chapter 6 proposes the implemented ’all-digital’ transmitter architecture. Of this architecture the requirements for the building blocks are studied and the power consumption of these digital circuits is estimated. In Chapter 7 the digital-to-analog converter used in this ’All-digital’ transmitter is analyzed and several models are derived to estimate the performance of the DAC in case of imperfections. A new framework is given for modeling and analysis of current steering DAC performance in the case of broadband signals, and especially at high sample rates. For such broadband signals, error mechanisms that create distortion around the mid-scale transitions are more dominant in the performance of the system than error mechanisms that create distortion at the extremes of the amplitude range. Using fully binary DACs or DACs with a low segmentation results in a higher distortion for signals that have wideband properties than for narrowband signals. When the DAC performance is affected by output conductance, a higher output conductance is allowed to achieve a similar performance for wideband signals than for a narrowband signal. Using these models an architecture for the DAC is selected and the measurement results of the realized DAC are shown. In Chapter 8 the IC implementations are being discussed. The transmitter concepts have been used in a rationalized manner to design and implement a 12-bit 2.8GS/s DAC in combination with digital signal processing that upsamples, combines and upconverts the carriers in a 90nm CMOS process, which serves as a vehicle IC to verify the validity of the ’all-digital’ transmitter concepts proposed in this thesis. Based on this DAC, three different versions of a complete ’all-digital’ transmitter, which consist of a combination of the digital signal processing and a DAC, were designed and implemented as ICs. The first two versions, the second being a redesigned version of the first one, use current mode logic for the digital signal processing, which is optimized to be able to run at the desired sample frequency of 2.8GS/s. Since the digital signal processing is made in current mode logic and synchronous with the DAC clock, no interference is observed. The third version uses static CMOS logic in combination with several methods, such as the use of poly-clock phases, to reduce the interference from the digital signal processing to the sensitive analog circuits. It is shown that the combination of these techniques to reduce the interference is sufficient to achieve the required performance. The preferred logic style to implement the digital circuits is standard CMOS logic, which is efficient in terms of power consumption and effort to implement the digital circuits. The proposed multi-carrier transmitter architecture is compared against the traditional multi-carrier transmitter. It has been shown that the proposed multi-carrier DOCSIS transmitter can be more power and area efficient when multiple channels are being broadcasted than multiple traditional DOCSIS transmitters that have their outputs combined. In the case of 64 channels the expected reduction in the power consumption is more than 90%.
8 citations
Cites background from "Highly Linear Mixer for On-chip RF ..."
...Conversion loss The theoretical conversion loss of an ideal passive mixer without the switch resistance is equal to [61]...
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01 Jan 2016
TL;DR: In this article, a highly linear passive attenuator and mixer were designed to be used in a wide-band Transmission Observation Receiver (TOR), which is a low IF receiver that accepts RF frequencies from 2GHz to 7GHz, and produces corresponding IF bandwidths of 280MHz to 990MHz using low side LO injection.
Abstract: In this thesis work, a highly linear passive attenuator and mixer were designed to be used in a wide-band Transmission Observation Receiver (TOR). The TOR is a low IF receiver that accepts RF frequencies from 2GHz to 7GHz, and produces corresponding IF bandwidths of 280MHz to 990MHz respectively, using low side LO injection. The dynamic range is maximized by using passive topologies for both the attenuator and the mixer. The system is dealing with different power levels ranging from -30dBm to +1dBm, and hence, a programmable digital step attenuator is used to attenuate large signals. It provides a maximum of 31dB of attenuation in 1dB steps. Different mixer architectures were compared, including CMOS mixer, mixer with dummy switches and quadrature mixer. Also, the performance of the mixer in both voltage mode and current mode was investigated. A double balanced passive mixer in voltage mode, with dummy switches was adopted in the final system since it proved to be the best in terms of meeting the requirements. The work was carried out in Ericsson in Lund, using Cadence, 65nm process. The circuit is true differential and it uses a supply voltage of 1.2V. The final results show a spurious free dynamic range of higher than 85dBc, minimum in band IIP3 of +15dBm , maximum IIP3 of +50dBm and a worst input return loss of less than -10dB. The amplitude and phase precision over the observation bandwidth were quite good, a worst phase error of less than 3 degrees was recorded and an amplitude error of 0.5dB. (Less)
3 citations
Cites background from "Highly Linear Mixer for On-chip RF ..."
...Conversion gain of this mixer is independent of the bias current [10]....
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...One of the disadvantage in such mixers is the need of large LO drive signal to turn the MOS switches on/off [10]....
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...The drain-source of passive mixers transistors are slightly biased with positive VDS for optimum conversion loss and optimized IMD performance [10]....
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References
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TL;DR: A multistandard architecture for a fully-integrated CMOS receiver is proposed, likely to all be present in the "universal" terminal of the future, enabling global roaming and wireless connectivity.
Abstract: In the recent past, there has been an evolution in wireless communications toward multifunctions and multistandard mobile terminals. Reducing the number of external components to a minimum is key when the same mobile terminal has to process several different standards. Highly integrated solutions in low-cost silicon technologies are thus required. Zero-IF and low-IF receiver architectures are most suitable for a high level of integration. This paper presents a review of global system for mobile communications, universal mobile telecommunication system, Bluetooth, and wireless local area network (IEEE802.11a, b, g and HiperLAN2) standards, likely to all be present in the "universal" terminal of the future, enabling global roaming and wireless connectivity. The various standards are analyzed in order to find the optimal architecture and the building-block specifications for the receive section, with particular care to the RF front-end. State-of-the-art solutions are discussed, with emphasis on direct conversion CMOS implementations. A multistandard architecture for a fully-integrated CMOS receiver is proposed.
295 citations
TL;DR: The nonlinearity behavior of CMOS current-switching mixers is investigated by treating the mixer as a periodically-time-varying weakly nonlinear circuit and the significance of a physical transistor model for reliable distortion simulation is demonstrated.
Abstract: The nonlinearity behavior of CMOS current-switching mixers is investigated. By treating the mixer as a periodically-time-varying weakly nonlinear circuit, we study the distortion-causing mechanisms and we predict the mixer distortion performance. Normalized graphs are provided from which the designer can readily estimate the mixer nonlinearity for particular process and design parameters. A simple CMOS transistor model appropriate for our calculations, which also takes into account deviation from the square law is adopted. The significance of a physical transistor model for reliable distortion simulation is demonstrated. The prediction of our analysis is compared with simulation results and with experimental data.
234 citations
13 Sep 2004
TL;DR: An EDGE transmitter, using a non-linear GSM type PA, is presented, and a dual feedback loop ensures robust performance even under VSWR variations.
Abstract: An enhanced data-rates for GSM evolution (EDGE) transmitter using a nonlinear GSM-type PA is presented. It is based on a novel polar loop architecture that employs separate feedback control of the amplitude and the phase of the output signal. With this approach, the problems with AM-to-PM as well as AM-to-AM of the nonlinear PA are essentially eliminated. In addition, this architecture allows for a large dynamic output power control range, as required by the GSM specification. The transmitter uses a standard I/Q interface and does not require the extraction of amplitude and phase modulation in the digital domain. The dual feedback loop ensures robust performance even under voltage-standing wave ratio variations without using an isolator. No external PA filtering is required to meet the transmitter noise in the receive band. The EDGE spectral mask is met with an rms error vector magnitude of <3% at 29 dBm at the antenna, corresponding to 2 dB above nominal maximum output power. There is no mode change between GMSK and EDGE, and the transmitter operates seamlessly in multislot Enhanced General Packet Radio Service. The polar modulation transmitter meets or exceeds the GSM-type approval requirements for both EDGE and GMSK in quad band (850/900/1800/1900 MHz).
183 citations
TL;DR: In this paper, the low voltage operation of a doubly balanced Gilbert mixer fabricated in a 0.8/spl mu/m CMOS process and operating as both a down-converter and an up-converster was demonstrated.
Abstract: This paper demonstrates the low voltage operation of a doubly balanced Gilbert mixer fabricated in a 0.8-/spl mu/m CMOS process and operating as both a down-converter and an up-converter. As a down-converter with an RF input of 1.9 GHz, the mixer has a single sideband noise figure as low as 7.8 dB and achieved down-conversion gain for supply voltages as low as 1.8 V. As an up-converter, the mixer demonstrates 10 dB of conversion gain at an RF frequency of 2.4 GHz with an applied local oscillator (LO) power of -7 dBm and LO-RF/LO-IF isolation of at least 30 dB. Up-conversion gain was achieved over a 5-GHz bandwidth and at supply voltages as low as 1.5 V. The mixer presented demonstrates the lowest single side band noise figure for a CMOS doubly balanced down-converting mixer and the highest frequency of operation for a mixer fabricated in CMOS technology to date.
182 citations