Hot-electron-induced MOSFET degradation—Model, monitor, and improvement
TL;DR: In this paper, a physical model involving the breaking of the ≡ Si s H bonds was proposed to explain the observed time dependence of MOSFET degradation and the observed channel field.
Abstract: Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with physical model involving the breaking of the ≡ Si s H bonds. The device lifetime τ is proportional to I_{sub}^{-2.9}I_{d}^{1.9}\Delta V_{t}^{1.5} . If I sub is large because of small L or large V d , etc., τ will be small. I sub (and possibly light emission) is thus a powerful predictor of τ. The proportionality constant has been found to vary by a factor of 100 for different technologies, offering hope for substantially better reliability through future improvements in dielectric /interface technologies. A simple physical model can relate the channel field E m to all the device parameters and bias voltages. Its use in interpreting and guiding hot-electron scaling are described. LDD structures can reduce E m and I sub and, when properly designed, reduce device degradation.
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IBM1
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.
2,680 citations
TL;DR: In this article, the degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model for both channel types using the charge-pumping technique.
Abstract: A model is derived using the charge-pumping technique for the evaluation of the interface characteristics, in combination with the behavior of the drain and the substrate currents after degradation For n-channel transistors the degradation is mainly caused by the generation of interface traps Only in the region of hole injection (V/sub g/ approximately=V/sub t/) is the degradation dominated by the trapped holes, which mask the effect of the generated interface traps The degradation of p-channel transistors, although completely different at first sight, occurs by the same mechanisms For this case, the degradation is caused by trapped negative charge, which masks the influence of the interface traps The latter are nevertheless generated in comparable amounts as in n-channel transistors Based on these insights, improved procedures for accelerated-lifetime experiments are proposed for both channel types Finally, the peculiar degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model >
415 citations
TL;DR: In this paper, the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications is examined.
Abstract: This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.
384 citations
TL;DR: In this paper, the authors describe the latest and most advanced surface potential-based model jointly developed by The Pennsylvania State University and Philips, which includes model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources.
Abstract: This paper describes the latest and most advanced surface-potential-based model jointly developed by The Pennsylvania State University and Philips. Specific topics include model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources. The emphasis of this paper is on incorporating the recent advances in MOS device physics and modeling within the compact modeling context
358 citations
Cites methods from "Hot-electron-induced MOSFET degrada..."
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TL;DR: A unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects is presented, and it is demonstrated that the proposed method very well predicts the degradation.
Abstract: Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current Isub, which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this paper, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65-nm technology. By benchmarking the prediction of circuit performance degradation with the measured ring oscillator data and simulations of an amplifier, we demonstrate that the proposed method very well predicts the degradation. For 65-nm technology, NBTI is the dominant reliability concern, and the impact of CHC on circuit performance is relatively small.
333 citations
References
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TL;DR: In this article, a simplified model of secondary ionization, avalanche breakdown and microplasma phenomena in p-n junctions was proposed, in which holes and electrons have identical properties described by four constants: generation of highest energy or Raman phonons, energy E R and mean-free-path L R ; ionization or electron-hole pair production, threshold carrier energy E i and mean free path L i.
Abstract: The phenomena of secondary ionization, avalanche breakdown and microplasma phenomena in p - n junctions are analyzed using a simplified model in which holes and electrons have identical properties described by four constants. Only two scattering processes for carriers are considered, each having two constants: generation of highest energy or Raman phonons, energy E R and mean-free-path L R ; ionization or electron-hole pair production, threshold carrier energy E i and mean-free-path L i . E R is determined from neutron scattering data; E R = 0·063 eV for Si and 0·037 eV for Ge. The other three constants are adjustable. E i and L i / L R = r are chosen to fit data on quantum yield for photons with 1 hv Q = 3−2 exp (E g +2E i −hv) 2rE R . For silicon this gives E i = 1·1 eV (which is equal to the energy gap E g ) and r = 17·5. For germanium E i is also about 1·1 eV and r = 57. The simple model predicts that the ionization coefficient α ( F ) varies with field F as (qF rE R ) exp − (E i qL R F ) which is in good agreement with data for electrons in silicon if L R is set equal to 50 A. The model predicts an energy per pair for ionization by high-energy particles of about 2·2 E i + rE R which is in good agreement with measured values. It also predicts a hot-carrier random energy of about 0·2 eV for F = 400,000 V/cm, which agrees with the spectra of hole-electron recombination in microplasmas. Thus the three adjustable constants permit fitting six pieces of experimental data in four independent experiments in spite of the fact that the intricacies of the band structure are disregarded. The effects of statistical spatial fluctuations of donor and acceptor ions are considered and it is concluded that these will be randomly distributed according to a Poisson distribution. This randomness leads to a characteristic fluctuation voltage (qF B K) 1 2 − 0·3 V for silicon where F B is the breakdown field, and the dielectric constant K = 1·04 × 10 −12 F/cm for silicon. The effect of these fluctuations is to produce local regions in a p - n junction with breakdown about 0·7 V lower than the average in uncompensated material. The fluctuations of voltage are larger by [(N d +N a ) (N d −N a )] 1 2 in compensated material. The fluctuations can increase the apparent ionization coefficient substantially. Microplasma effects are considered and it is shown that in a junction with only the Poisson fluctuations the microplasma should be stabilized by an apparent series resistance due to space charge of magnitude 1 υ max K − 10 5 Ω where υ max = (E R m ∗ ) 1 2 is the limiting drift velocity. This is much larger than the spreading resistance term of magnitude 1 μF B K − 2000 Ω . It is concluded that typical noisy microplasma phenomena are probably associated with localized structural defects probably having two characteristics: (1) they increase the effect ionization coefficient to a value greater than 10 5 cm −1 over a region less than 10 −5 cm long; (2) they have a mechanism for capturing charge which increases the field once the microplasma has formed. Small SiO 2 precipitates and dense arrays of dislocations appear to have the requisite properties. Metal precipitates in the space-charge layer produce “soft” reverse characteristics with localized currents of the form V 6±1 .
835 citations
TL;DR: A detailed study of the increase of the number of surface traps in MOS structures after NBS at temperatures (25-125°C) and fields (400-700 MV/m) comparable to those used in MNOS devices is presented in this article.
Abstract: One of the most important degradation effects observed in MNOS memory transistors is a negative shift of the threshold window. This negative shift is caused by a strong increase of the density of Si‐SiO2 surface traps. This effect has been proposed to be caused by the same effect that is observed in MOS devices subjected to negative‐bias stress (NBS). In this paper, a detailed study of the increase of the number of surface traps in MOS structures after NBS at temperatures (25–125 °C) and fields (400–700 MV/m) comparable to those used in MNOS devices is presented. Two different behaviors are observed. At low fields the surface‐trap density increases as t1/4 and at high fields it increases linearly with the stress time t. The low‐field behavior is temperature and field dependent and the zero‐field activation energy is determined to be 0.3 eV. The high‐field behavior is strongly field dependent but independent of temperature. A physical model is proposed to explain the surface‐trap growth as being diffusion ...
678 citations
TL;DR: In this article, an empirical model for device degradation due to hot-carrier injection in submicron n-channel MOSFET's is presented, and the relationship between device degradation, drain voltage, and substrate current is clarified on the basis of experiments and modeling.
Abstract: An empirical model for device degradation due to hot-carrier injection in submicron n-channel MOSFET's is presented. Relationships between device degradation, drain voltage, and substrate current are clarified on the basis of experiments and modeling. The presented model makes it possible to predict the lifetime of submicron devices by determining a certain criterion, such as taking a V th shift of 10 mV over ten years as being allowable. This could also provide quantitative guiding principles for devising "hot-carrier resistant" device structures.
539 citations
TL;DR: In this article, it was shown that the number of light spots increases with the current rather than individual spots growing brighter, and that all the breakdown current is carried through the junction by these localized light-emitting spots.
Abstract: Visible light is emitted from reverse-biased silicon $p\ensuremath{-}n$ junctions at highly localized regions where avalanche breakdown is taking place. The emission occurs in both grown and diffused junctions. By using junctions diffused to a depth of only 2 microns below the crystal surface, it was established that the light sources are randomly spaced over the whole area of the junction as well as around the periphery where the junction intercepts the surface. The light sources are too small to be resolved under a high-power microscope. Their sites are reproducible with current cycling and their intensity and color are relatively insensitive to the field distribution, to the junction width, and to temperature. The number of light spots increases with the current rather than individual spots growing brighter. It is concluded that all the breakdown current is carried through the junction by these localized light-emitting spots.The spectral distribution of the light is continuous with a long tail extending to photon energies greater than 3.3 ev. It is concluded that recombination between free electrons and free holes within the junction region is responsible for the light at the shorter wavelengths, the carrier energies in excess of the energy gap being supplied by the field. At longer wavelengths there appears to be a considerable contribution to the emission from intraband transitions.A tentative figure for the emission efficiency over the visible spectrum is one photon for every ${10}^{8}$ electrons crossing the junction. The recombination cross section required is reasonable, being about ${10}^{\ensuremath{-}22}$ ${\mathrm{cm}}^{2}$.
449 citations
TL;DR: In this article, a series of experiments designed to characterize the charging effect of thermal SiO2 films with water was conducted. And they found that if water is diffused into a SiO 2 film, water related centers are formed which act like electron traps with capture cross section of approximately 1.5 × 10−17 cm2.
Abstract: When electron currents flow in thermal SiO2 films which have been exposed to water, a buildup of negative charge occurs in the oxide. This paper describes a series of experiments designed to characterize this charging effect. It is found that if water is diffused into a SiO2 film, water related centers are formed which act like electron traps with capture cross section of approximately 1.5 × 10−17 cm2. Experiments are described which show that when one of these centers captures an electron, atomic hydrogen is released which diffuses away and escapes or reacts and a stable negative charge is left behind. Electrochemical charging effects of this type have not previously been considered, although they may play a very important role in some semiconductor device failure effects.
400 citations