Journal ArticleDOI
HSTL IO Standards Based Processor Specific Green Counter Design on 90nm FPGAAbhay Saxena
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TLDR
The researchers have used High Speed Transceiver Logic for the purpose of energy efficient counter design on Spartan3 (90nm) FPGA using VHDL (VHSIC Hardware Description Language) hardware description language and the Xilinx ISE simulator for the analysis and synthesis of counters.Abstract:
Extending battery life and increase in portability of modern electronic devices and gadgets are the main motives behind the Green Computing which is also known by similar terms like energy efficient design or low power design or green design. Such efficiency is only possible if all the components of processor are also energy efficient. In this work, the researchers tried to analyze the energy optimization possibility in counter design by selection of energy efficient IO standards. The researchers had used High Speed Transceiver Logic for the purpose of energy efficient counter design on Spartan3 (90nm) FPGA (field-programmable gate array) using VHDL (VHSIC Hardware Description Language) hardware description language along with the Xilinx ISE simulator for the analysis and synthesis of counters. Spartan 3 with 90 nm low power is used to achieve substantial power savings. Here, researchers have used five different HSTL IO standards for this work. The standards used are HSTL_I, HSTL_III, HSTL_III_18, HSTL_III_DCI and HSTL_II_18. With these sets of IO standards, Researchers had run their counter design on various device operating frequencies (1.0 GHz to 4.0 GHz). The results clearly indicate that this dynamic frequency (1.0 GHz in lieu of 4.0 GHz) scaling had saved 45% of total power.read more
Citations
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Journal ArticleDOI
Scaling of Output Load in Energy Efficient FIR Filter for Green Communication on Ultra-Scale FPGA
Bishwajeet Pandey,Nisha Pandey,Amanpreet Kaur,D. M. Akbar Hussain,Bhagwan Das,Geetam Singh Tomar +5 more
TL;DR: Along with IOs power and total on-chip power, the model has also analyzed Off-chip device power, junction temperature, thermal margin, and different dynamic power likes Signal power, logic power, and DSP power.
Journal ArticleDOI
Capacitance Scaling Based Low Power Comparator Design on 28nm FPGA
TL;DR: This work scaled down the capacitance from 512pF to 32pF at various fixed frequency and implemented on 28 nm Artix7 FPGA with I/O Power & Leakage Power.
Journal ArticleDOI
SSTL Based Energy Efficient FIFO Design for High Performance Processor of Portable Devices
TL;DR: The FIFO (First In First Out) circuit is designed and calculated its total power dissipation at different-different families of SSTL with frequency scaling techniques and is based on 28 nm kintex-7 FPGA family.
Proceedings ArticleDOI
SSTL IO Based WLAN Channel Specific Energy Efficient RAM Design for Internet of Thing
TL;DR: The objective is to come up with High Performance RAM design for IOT based processor by reducing the power consumption and it is thought that the application of this design will definitely help to design in futuristic Iot based processor development.
Journal ArticleDOI
Designing Power Efficient Fibonacci Generator Using Different FPGA Families
TL;DR: In consideration to wireless communication Fibonacci number is used to generate WPA and WPA2 (Wi-Fi Protected Access) key and here, in this work, green fibonacci Generator under different FPGA families are designed.
References
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The design of high speed UART
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TL;DR: The simulated waveforms in this paper have proven the reliability of the VHDL implementation to describe the characteristics and the architecture of the design UART with baud rate generator.
Proceedings ArticleDOI
Energy efficient design and implementation of ALU on 40nm FPGA
TL;DR: There is 67.04% dynamic power reduction with LVCMOS12 when the authors migrate from 90-nm Spartan-3 FPGA to 40-nm Virtex-6FPGA, and there is 81.19%, 92.05% and 73.41% dynamicPower reduction in ALU with LVDCI IO standard in place of LVD CI_DV2, HSTL_I, and LVCmOS12 respectively.
Proceedings ArticleDOI
Low Power VLSI Circuit Design with Efficient HDL Coding
TL;DR: A four-bit unsigned up counter with an asynchronous clear and a clock enable is designed in Xilinx ISE 14.2 and implemented on high performance Virtex-6 FPGA, XC6VLX240T device, -1 speed grade, FFG1156 package and ML605 board and the experimental result shows the power analysis of both HDL mapping code.
Journal ArticleDOI
HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA
Shivani Madhok,Bishwajeet Pandey,Amanpreet Kaur,Mohamed Hashim Minver,Dil muhammed Akbar Hussain +4 more
TL;DR: Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper and can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius.
Proceedings ArticleDOI
Energy Efficient Counter Design Using Voltage Scaling on FPGA
TL;DR: Voltage scaling is used to make the counter design as an energy efficient design and it has been observed that when different powers have been measured at different frequencies and different voltages in case of counter the significant power dissipation is in case clocks and IOs.