Image Processing on a Custom Computing Platform
07 Sep 1994-pp 156-167
TL;DR: The Splash-2 custom computing platform is a general-purpose platform not designed specifically for image processing, yet it can cost-effectively deliver real-time performance on a wide variety of image applications.
Abstract: Custom computing platforms are emerging as a class of computing engine that not only can provide near application-specific computational performance, but also can be configured to accommodate a wide variety of tasks. Due to vast computational needs, image processing computing platforms are traditionally constructed either by using costly application-specific hardware to support real-time image processing, or by sacrificing real-time performance and using a general-purpose engine. The Splash-2 custom computing platform is a general-purpose platform not designed specifically for image processing, yet it can cost-effectively deliver real-time performance on a wide variety of image applications. This paper describes an image processing system based on the Splash-2 custom computing engine, along with performance results from a variety of image processing tasks extracted from a working laboratory system. The application design process used for these image processing tasks is also examined.
Citations
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TL;DR: This paper presents the high level, machine independent, algorithmic, single-assignment programming language SA-C and its optimizing compiler targeting reconfigurable systems, intended for Image Processing applications.
Abstract: This paper presents the high level, machine independent, algorithmic, single-assignment programming language SA-C and its optimizing compiler targeting reconfigurable systems. SA-C is intended for Image Processing applications. Language features are introduced and discussed. The intermediate forms DDCF, DFG and AHA, used in the optimization and code-generation phases, are described. Conventional and reconfigurable system specific optimizations are introduced. The code generation process is described. The performance for these systems is analyzed, using a range of applications from simple Image Processing Library functions to more comprehensive applications, such as the ARAGTAP target acquisition prescreener.
90 citations
Patent•
26 Feb 1996
TL;DR: In this article, the authors describe methods and apparatus for adaptable network processing having speed advantages often associated with hardware implementations of network processing code or logic, as is often achieved using ASICs, for example, but at the same time having reconfigurability advantages associated with software implementations of this code and logic, such as a field programmable gate array (FPGA) or a circuit using FPGAs.
Abstract: Processor methods and apparatus for adaptable network processing having speed advantages often associated with hardware implementations of network processing code or logic, as is often achieved using ASICs, for example, but at the same time having reconfigurability advantages often associated with software implementations of this code or logic Methods and apparatus are described for adaptable hardware devices, such as a field programmable gate array (FPGA) or a circuit using FPGAs, to execute network processing code or logic Methods and apparatus are described for using a software based device to program adaptable hardware devices to implement desired network processing code or logic
86 citations
19 Apr 2001
TL;DR: The hardware structure and application of a coarse-grained dynamically reconfigured hardware architecture dedicated to wireless communication systems and a motivation for choosing the concept of distributed arithmetic in reconfigurable computing is provided.
Abstract: This paper presents the hardware structure and application of a coarse-grained dynamically reconfigurable hardware architecture dedicated to wireless communication systems. The application tailored architecture, called DReAM (D_ynamically R_econfigurable Hardware A_rchitecture for M_obile Communication Systems), is a research project at the Darmstadt University of Technology. It covers the complete design process from analyzing the requirements for the dedicated application field, the specification and VHDL implementation of the architecture, up to the physical layout for the final chip. In the following we provide an overview of the major design stages, starting with a motivation for choosing the concept of distributed arithmetic in reconfigurable computing.
76 citations
05 Jul 2017
61 citations
16 Apr 1997
TL;DR: The paper discusses a mapping experiment where a linear-systolic implementation of an ATR algorithm is mapped to the SPLASH 2 platform, and the resulting design is scalable and can be spread across multiple SPLash 2 boards with a linear increase in performance.
Abstract: Automated target recognition is an application area that requires special-purpose hardware to achieve reasonable performance. FPGA-based platforms can provide a high level of performance for ATR systems if the implementation can be adapted to the limited FPGA and routing resources of these architectures. The paper discusses a mapping experiment where a linear-systolic implementation of an ATR algorithm is mapped to the SPLASH 2 platform. Simple column oriented processors were used throughout the design to achieve high performance with limited nearest neighbor communication. The distributed SPLASH 2 memories are also exploited to achieve a high degree of parallelism. The resulting design is scalable and can be spread across multiple SPLASH 2 boards with a linear increase in performance.
59 citations
References
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TL;DR: A technique for image encoding in which local operators of many scales but identical shape serve as the basis functions, which tends to enhance salient image features and is well suited for many image analysis tasks as well as for image compression.
Abstract: We describe a technique for image encoding in which local operators of many scales but identical shape serve as the basis functions. The representation differs from established techniques in that the code elements are localized in spatial frequency as well as in space. Pixel-to-pixel correlations are first removed by subtracting a lowpass filtered copy of the image from the image itself. The result is a net data compression since the difference, or error, image has low variance and entropy, and the low-pass filtered image may represented at reduced sample density. Further data compression is achieved by quantizing the difference image. These steps are then repeated to compress the low-pass image. Iteration of the process at appropriately expanded scales generates a pyramid data structure. The encoding process is equivalent to sampling the image with Laplacian operators of many scales. Thus, the code tends to enhance salient image features. A further advantage of the present code is that it is well suited for many image analysis tasks as well as for image compression. Fast algorithms are described for coding and decoding.
6,975 citations
"Image Processing on a Custom Comput..." refers methods in this paper
...A popular technique for generating these pyramids (known as Gaussian and Laplacian pyramids) is described in [10]....
[...]
Book•
01 Jan 1976
TL;DR: The rapid rate at which the field of digital picture processing has grown in the past five years had necessitated extensive revisions and the introduction of topics not found in the original edition.
Abstract: The rapid rate at which the field of digital picture processing has grown in the past five years had necessitated extensive revisions and the introduction of topics not found in the original edition.
4,231 citations
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
Abstract: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described. The PRISM approach adapts the configuration and fundamental operations of a core processing system to the computationally intensive portions of a targeted application. PRISM-1, an initial prototype system, is described, and experimental results that demonstrate the benefits of the PRISM concept are presented. >
415 citations
"Image Processing on a Custom Comput..." refers background in this paper
...There are many promising endeavors that focus on this issue [6,7,8]; the main emphasis of these are to automate to some degree the portions of the shaded region of Figure 2....
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05 Apr 1993
TL;DR: The architecture of Splash 2 is designed to accelerate the solution of problems which exhibit at least modest amounts of temporal or data parallelism, and has been shown to be effective on a variety of applications, including text searching, sequence analysis, and image processing.
Abstract: Splash 2 is an attached special purpose parallel processor in which the computing elements are user programmable FPGA devices. The architecture of Splash 2 is designed to accelerate the solution of problems which exhibit at least modest amounts of temporal or data parallelism. Applications are developed by writing behavioral descriptions of algorithms in VHDL, which are then iteratively refined and debugged within the Splash 2 simulator. Once an application is determined to be functionally correct in simulation, it is compiled to a gate list and optimized by logic synthesis. The gate list is then mapped onto the FPGA architecture by automatic placement and routing tools to form a loadable FPGA object module. A C language library and a symbolic debugger comprise the execution environment. The Splash 2 system has been shown to be effective on a variety of applications, including text searching, sequence analysis, and image processing. >
87 citations
"Image Processing on a Custom Comput..." refers background in this paper
...A more complete description of SPLASH hardware and software development environment can be found in [1,2]....
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10 Apr 1994
TL;DR: This paper describes the design and implementation of two image-processing algorithms using the SPLASH 2 custom computing platform, designed to operate at high speed and illustrated the efficacy of reconfigurable FPGA-based machines to image processing applications.
Abstract: This paper describes the design and implementation of two image-processing algorithms using the SPLASH 2 custom computing platform. SPLASH 2 is a reconfigurable system that can be tailored to perform a wide variety of tasks. The particular tasks discussed here are the Hough transform. A well-known technique for detecting lines in an image, and pyramid generation. The process of transforming a single image into a set of filtered images with successively lower spatial resolution. This paper describes how these computationally intensive processes have been mapped onto SPLASH 2 hardware. Both processes have been designed to operate at high speed. In particular, the generation of both Gaussian (low-pass) and Laplacian (band-pass) pyramids can occur concurrently in real time using images from a video camera, assuming the standard frame rate of 30 images per second. Results are presented to illustrate the efficacy of reconfigurable FPGA-based machines to image processing applications. >
58 citations