1
Immunity to Device Variations in a Spiking Neural
Network with Memristive Nanodevices
Damien Querlioz, Member, IEEE, Olivier Bichler, Philippe Dollfus, Member, IEEE, and Christian Gamrat
Abstract—Memristive nanodevices can feature a compact
multi-level non-volatile memory function, but are prone to device
variability. We propose a novel neural network-based computing
paradigm, which exploits their specific physics, and which has
virtual immunity to their variability. Memristive devices are used
as synapses in a spiking neural network performing unsupervised
learning. They learn using a simplified and customized “spike
timing dependent plasticity” rule. In the network, neurons’
threshold is adjusted following a homeostasis-type rule. We
perform system level simulations with an experimentally verified-
model of the memristive devices’ behavior. They show, on the
textbook case of character recognition, that performance can
compare with traditional supervised networks of similar complex-
ity. They also show that the system can retain functionality with
extreme variations of various memristive devices’ parameters (a
relative standard dispersion of more than 50% is tolerated on
all device parameters), thanks to the robustness of the scheme,
its unsupervised nature, and the capability of homeostasis.
Additionally the network can adjust to stimuli presented with
different coding schemes, is particularly robust to read disturb
effects and does not require unrealistic control on the devices’
conductance. These results open the way for a novel design
approach for ultra-adaptive electronic systems.
Index Terms—spiking neural networks, memristors, mem-
ristive devices, spike timing dependent plasticity, unsupervised
learning, neuromorphic
I. INTRODUCTION
M
EMRISTIVE nanodevices provide fantastic opportuni-
ties for microelectronics. They can indeed provide a
compact multi-level non-volatile memory function [1]. How-
ever, they are often subject to strong variability [2], [3], [4],
so that fully exploiting their potential would be easier with
architectures offering a strong immunity to device variations.
Spiking neural networks could provide a serious lead since
the brain itself relies on variable neurons and synapses [5]
and manages computational efficiency that outperforms man-
made systems. This idea takes particular meaning in that many
groups (constituting the “neuromorphic” community) already
imitate the brain with electronics, using Complementary Metal
Oxide Semi-conductor (CMOS) circuits to model its spiking
neurons and synapses. These works, however, are often limited
by the number of implementable synapses: implementing
D. Querlioz and P. Dollfus are with Institut d’Electronique Fondamentale;
Univ. Paris-Sud, CNRS; 91405 Orsay France.
O. Bichler and C. Gamrat are with CEA, LIST, Laboratory for Enhancing
Reliability of Embedded Systems , 91191 Gif-sur-Yvette, France.
This work was supported by the European Union through the FP7 Project
NABAB (Contract FP7-216777) and by CNRS/INSIS (PEPS Synapse).
Copyright (c) 2013 IEEE. Personal use is permitted. For any other
purposes, permission must be obtained from the IEEE by emailing pubs-
permissions@ieee.org.
plastic synapses requires many transistors [6], [7]. Memristive
nanodevices could provide the compact synapses required to
advance neuromorphic circuits. In recent years several classes
of them have indeed emerged, as e.g. resistive RAMs and
memristors [1], [2], or adaptive transistors [8], [3]. It has
been suggested [9], [10], [11], [12], and shown experimentally
[13], [14], [15], [16], [17], [18], that such devices could
reproduce a learning rule of biological synapses – spike timing
dependent plasticity (STDP) [19], [20] – that is believed to be
a foundation of learning in the brain [21]. A system consisting
of nanoscale synapses and CMOS neurons could be a major
breakthrough in computing, allowing cognitive-type tasks with
high efficiency.
This idea is currently receiving considerable interest [22],
[23], [24], [25]. However, its sustainability is still to be
demonstrated, especially with regards to the variability issue
that is common to all memristive technologies [26], [27], [4].
It is also not clear if biological STDP is the best approach
for electronics, the constraints of which differ strongly from
Biology’s.
In this paper, system simulations introduce quantitative
results in terms of computing performance and robustness
to variability. We exploit a simplified and customized STDP
scheme for memristive devices, which is key to achieve effec-
tive learning with extreme robustness to memristive devices’
variability. It is associated with the use of unsupervised learn-
ing, and of a homeostasis-type mechanism. We describe the
required technology and architecture (section II) and perform
system-level simulations on a standard database of machine
learning [28] that show the potential of the approach and
its robustness. The system consists of an unsupervised layer
that extracts features of the inputs using a simplified spike
timing dependent plasticity (section III). The network perfor-
mance compares favorably with traditional – but supervised –
networks with similar numbers of adjustable parameters and
achieves excellent tolerance to various memristive devices’
parameters variability. Finally, the robustness of the network to
other device nonidealities (read disturb and limited resolution
effects) is established (section IV).
Partial and preliminary results have appeared in [12]. This
papers adds new discussions and results, especially the plau-
sibility of the device model with regards to measurements of
real devices, adaptations of the programming scheme, and the
impact of diverse device nonidealities. Other proposals have
been made to exploit variable adaptive devices in the context
of nanotechnological implementations. Most proposed archi-
tectures rely on reconfigurable logic [29] or on state-based
supervised neural networks [30], [31]. In the first approach
2
784
CMOS
input
neurons
CMOS output neurons
(integrate & fire neurons)
nanodevice
Lateral inhibition
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ŝŶŚŝďŝƚŝŽŶ
Figure 1. Circuit topology. Wires originate from CMOS input layer
(horizontal black wires) and from the CMOS output layer (vertical gray wires).
Memristive nanodevices are at the intersection of the horizontal and vertical
wires.
variability is addressed through error mapping and redundancy,
in the second case through a standard neural network approach
using supervised learning based on error gradient descent.
Our approach of using unsupervised learning with asyn-
chronous spiking neural networks to tackle the variability issue
of nanodevices is original and takes inspiration from recent
ideas in computational neuroscience and neural networks [32],
[33], [34]. Different works have been published that go into
that direction. As mentioned above, several proposals exist
to use memristive devices for STDP [10], [9], [11], [35]. In
this paper we use a simplified STDP scheme that is easier to
implement. Additionally, we propose to give to the neurons a
homeostasis property and that is shown to be essential for
the robustness of the scheme to variations. One work had
already shown that memristive devices with STDP could allow
the emergence of receptive fields in a variability-compatible
unsupervised approach and synchronous neurons [36]. Our
work uses asynchronous designs, like the ones used in the
neuromorphic community [6], [7], and performs full learning
on a standard dataset. Finally, an alternative way to allow
learning with memristive devices in a variability-compatible
way can be to use all digital designs [22]. This requires
more devices per synapses [37]. In this paper we show that
variation-tolerance can be retained by using nanodevices with
continuous variation of the conductance.
II. ARCHITECTURE AND IMPLEMENTATION OF THE
NETWORK
We first introduce the architecture that we propose for
our classifier system. CMOS input and output “neurons” are
connected by the nanodevices that act as synapses. It is natural
to lay out the nanodevices in the widely studied crossbar as
illustrated on Fig. 1, where CMOS silicon neurons and their
associated synaptic driving circuitry are the dots, the squares
being the nanodevices. The synapses indeed act as adaptive
resistors. With the crossbar layout, if several synapses are ac-
tive at the same time (i.e. receiving voltage spikes), the output
receives directly the sum of the currents flowing through the
synapses. In a more futuristic design, the system could also be
laid out in a CMOL architecture where nanodevices crossbar
is fabricated on top of the CMOS neurons and driving circuits
[30].
Voltage applied on the device…
…if Output spikes while Input is still active
…if Output spikes alone
V
T+
V
T-
Voltage
Time
Voltage
Time
Input spikes
Output spikes
V
input
Time
V
output
Time
(a)
(b)
(c)
(d)
V
T-
V
T+
Figure 2. Pulses for simplified STDP (voltage pulses as a function of time).
When an input neuron spikes, it applies an Input pulse (a) to the nanodevices to
which it is connected. When an output neuron spikes it applies an Output pulse
(b) to the nanodevices to which it is connected. When the voltage applied on
the device (difference between the voltages applied at the two ends (c) or (d))
reaches V
T +
or V
T −
, its conductance is increased or decreased, respectively.
This kind of connectivity corresponds to a feed-forward
architecture in a neural network. Of particular interest, in the
case of our network, it limits the sneak path issue because
both programming and reading are performed in parallel.
This issue usually limits the competitiveness of crossbars [38]
and requires complex counter-measures like complementary
resistive switches [39], or the use of nonlinear devices [40].
As a replacement of memristive devices, the architecture
may also exploit phase change memories associated in “2-
PCM” circuits as evidenced experimentally in [14], [18], [41],
which has the advantage of technological maturity.
The input neurons present the stimuli as asynchronous volt-
age spikes using several possible coding schemes described
in section III-C. Spiking rate is proportional to stimulus
intensity. These stimuli may originate for example directly
from a spiking retina [42] or cochlea [43] designed in the
neuromorphic community that present data as asynchronous
spikes, similarly to their biological counterparts.
As a result of learning, the output neurons should become
selective to the different stimuli classes that are presented in a
fully unsupervised manner: the output neurons should develop
selectivity to specific features contained in the input patterns.
The learning rule of the nanodevices needs to be fully local to
be implementable in the crossbar architecture. The behavior of
the neurons needs to be simple to make it easy to implement
in a compact way. We now describe how this can be achieved.
The next subsections describe the different elements into
more details. The synapses learn using a simplified STDP
scheme (section II-A1). The output neurons behave as leaky
integrate-and-fire neurons (section II-B1) and have a home-
ostasis property (section II-B3). They are also connected by
inhibitory connections using diffuser networks (section II-B2).
3
…if Output spikes while Input is still active
V
T+
Voltage
Time
Input Neuron active
Figure 3. Pulses for simplified STDP (voltage pulses as a function of time).
-100 -50 0 50 100
-60
-40
-20
0
20
40
60
80
100
120
Dt = t
pre
- t
post
(s)
Exp. data [Bi&Poo]
LTP
LTD
LTP simulation
LTD simulation
Biology
Classical rule
Simple rule
Dt = t
input
- t
output
(s)
Figure 4. The simplified STDP rule, compared with the standard biological
STDP rule.
A. Synaptic behavior
1) Simplified STDP learning: In this work, the synapses
are acting in two ways. They are variable resistors and thus
transmit spikes with a variable conductance (which plays the
exact role of a synaptic weight). Additionally, they adapt their
conductance depending on the activity of the neurons to which
they are connected, which provides the foundation of learning
by the system.
The memristive nanodevices are programmed as follows.
When being applied a positive voltage pulse higher than a
threshold V
T +
, they increase their conductance. When applied
a voltage pulse smaller than a negative threshold V
T −
, they
decrease their conductance [13], [10]. Previous works have
shown that memristive devices can implement spike timing
dependent plasticity (STDP), a learning rule used by brain
synapses [13], [14], [15], [9], [11], [10], [16], [17], [35]. These
works focused on faithful imitation of Biology. In this work,
we focus on proposing simpler scheme, targeted toward pattern
extraction, as illustrated in Figure 2.
• When an input neuron spikes, it applies a long voltage
pulse to its synapses (Input pulse, Figure 2(a)). This
voltage is high enough to drive some current into a
memristive device, but not enough to reprogram it. This
current is integrated by the output neurons (resistor role
of the synapse). If several synapses connected to the same
output neuron are active at the same time their currents
are summed.
• When an output neuron spikes, it applies a pulse that is
a succession of a negative bias and of a positive bias
(Output pulse, Figure 2(b)). If no Input pulse is being
applied to the device, only the second part reaches a
threshold and the conductance of the synapse is decreased
by δG
m
(Figure 2(d)). However, if the input neuron had
spiked recently, and the Input pulse is still being applied
on the other end of the device, the voltage applied on the
device actually increases its conductance by δG
p
((Figure
2(c)).
This simple learning rule, easily implemented with nanode-
vices, is the ground for learning. Compared with the purely
bioinspired and more complex scheme introduced in [9], no
delay matching is necessary between the Input and Output
synaptic waveforms, which should make the driving circuitry
much easier to design.
The way this simple learning rule works is straightforward.
When an output neuron declares a spike (at time t
spike
), it
increases by δG
p
the conductance of the synapses connected
to input neurons that spiked recently (from t
spike
− t
P RE
to t
spike
, if t
P RE
is the duration of the Input pulse), and
decreases by δG
m
the conductance of the synapses that did
not. This increases the sensitivity of the neuron to the specific
pattern that activated it, making it more likely to spike for a
similar (correlated) pattern in the future. This process – that
works surprisingly well in practice, as we show in this paper
– has been partially theorized in [34]. A comparison with the
traditional biological STDP scheme is presented in Figure 4.
A disadvantage of this rule is the long Input pulse, which
drives current for a long time, and thus increases power
consumption. If it becomes significant, a low power version of
the learning rule is possible and illustrated in Figure 3, for the
cost of limited added complexity. The input neuron does not
apply a voltage pulse during the whole time it is active, but
only at the beginning to drive current into the output neuron.
Additionally, as soon as one of the output neuron becomes
active, a signal is sent back to the input neurons, which apply
a short Input pulse again if they are still active. This lower
power version of the learning scheme is more realistic with
most current technologies like [13], [14].
2) Memristive devices modeling: To model the conductance
increments and decrements in our system simulations, we
use the model introduced in [44]. It takes inspiration from
experimental memristive devices measurements [13], [15]. An
increase in the conductance is modeled by the equation:
δG
p
= α
p
e
−β
p
G−G
min
G
max
−G
min
. (1)
Similarly, a decrease is modeled by:
δG
m
= α
m
e
−β
m
G
max
−G
G
max
−G
min
. (2)
The exponential factor expresses the fact, observed in most
memristive technologies, that a given voltage pulse has a
reduced effect on the device conductance if applied several
times [13], [15], [14]. Agreement with the experimental data
of [13] is presented in Figure 5. The parameters α
p
, α
m
, β
p
,
β
m
depend heavily on the Input and Output pulse voltages
that are chosen. These parameters, as well as minimum and
maximum conductances G
min
and G
max
are subject to device
variability in real devices.
B. Output neurons
1) Output neurons’ dynamics: Exploiting the devices re-
quires connecting them to processing units – silicon neurons
able to process and generate spikes in a bioinspired manner
4
0
20
40
0 20 40 60 80
100
Pulse number
0
20
40
0 20 40 60 80 100
Pulse number
(a) (b)
Figure 5. Evolution of the conductance for the devices from [13], fitted with
equations 1 and 2. (a) device conductance (measured at 1V ) after each pulse
in a serie of potentiating (V = −3.2V ) pulses. (b) same with depressing
(V = 2.8V ) pulses. Diamond: experimental data, reproduced from [13]. Full
line: equations 1 and 2.
by integration of their input. We call X the state variable (a
current or a voltage, equivalent of the biological “membrane
potential”) of the neuron (expressed in normalized unit where
the maximum value of the state variable X is 1). Neurons
are leaky integrate-and-fire type, which is meant to solve the
simple following equation. :
τ
dX
dt
+ gX = γI
input
(3)
where τ is a leak time constant, and g and γ are constants.
I
input
represents the current flowing through the line of the
crossbar connected to the neuron:
I
input
=
X
j
I
j
(4)
where I
j
are the currents flowing through each memristive
device j connected to output neuron.
The neuron declares a spike if X reaches a given threshold
X
th
, in which case X is reset to zero.
An approach widely studied in the neuromorphic com-
munity is to use analog circuits (generally with transistors
operating in the sub-threshold regime) able to receive and
generate asynchronous spikes [6], [7] to design such neurons.
This kind of CMOS design is particularly low power, because
most transistors operate in the subthreshold regime, and thanks
to the use of asynchronous computation. Though smaller than
in nanodevices, variability is also a problem for such transistor
designs. It is a challenge for any neuromorphic design [43]
and will become even more crucial when scaling to modern
technology. Digital designs may also be used that do not suffer
from variability directly but may have higher area and power
requirements [45].
2) Output neurons’ lateral inhibition : When an output
neuron spikes, it sends inhibitory signals to the other output
neurons of the layer that prevent them from spiking during
the inhibition time and resets their potential to zero. With this
inhibition, the network is reminiscent of a Winner-Takes-All
topology [34].
More precisely, when an output neuron spikes, the state
variable X of the other output neurons is reset to zero during
a time t
inhibit
.
Figure 6. Conductances (weights) learned in a simulation with 10 output
neurons. Red is maximum conductance, blue is minimum conductance.
X = 0 if t
spike
< t < t
inhibit
. (5)
In hardware, this inhibition between the neurons can be
implemented in a compact way through diffuser networks as
in [6], which require a minimum number of transistors.
3) Homeostasis : A final issue for the architecture is the
adjustment of the neurons’ threshold. Simple algorithms exist
for traditional (non spiking) artificial neuron networks, but
they do not work directly for spiking neurons. A bioinspired
original route is homeostasis [5]. A target activity is defined
for the neurons (i.e. a number of times an output neuron
should spike over an extended period of time, like 100
digits presentation). Regularly the threshold of the neuron is
increased if the average activity of the neuron is above the
target, and decreased if it is below.
dX
th
dt
= γ (A − T ) , (6)
where A is the mean activity (or firing rate) of a neuron, T
is the target activity, and γ is a multiplicative positive constant.
This ensures that all the output neurons are used and
adjust the neurons’ thresholds to the stimuli for which they
become specialized. In neuromorphic hardware, homeostasis
has been implemented with analog memories like in [46] or
could be implemented digitally. The advantage inherent in this
technology is evidenced in this paper in section III-B.
C. Simulations of the System
In this paper, all simulations are system-level and are based
on a C++ special purpose code (“Xnet”) [47], [12]. The code is
event-based for simulation performance and runs on traditional
central processing units (CPUs). Simulation parameters as
introduced above are τ = 100 ms, g = 1, X
th
= 0.5 (nor-
malized unit), inhibition time t
inhibit
= 10 ms, α
p
= 10
−2
,
α
m
= 5 · 10
−3
, G
min
= 10
−4
, G
max
= 1 (normalized units
where the mean of the maximum conductance value is 1),
β
p
= 3.0, β
m
= 3.0. The width of the Input pulses is 25 ms.
Parameter variations are introduced around all the parameters
using Gaussian random numbers (the value of their standard
deviation is given in Section III). The initial conductances
are selected randomly around mid-range (0.5). The stimuli are
applied using the coding schemes described in section III-C.
The two variations of voltages pulses (Figures 2 and 3)
gave identical performance in terms of recognition rate. All
the results presented in the paper use the pulses of Figures 2.
For demonstration of the concept, in this paper we use
the widely studied case of handwritten number recognition.
5
50
60
70
80
90
100
0 100 200 300 400 500
Number of output neurons
Figure 7. Recognition rate on the test dataset as a function of the number of
output neurons (simulations were repeated ten times, error bar is one standard
deviation).
The MNIST database is used, which consists in handwritten
number of 28 × 28 pixels by 250 writers [28].
In order to achieve learning, we present the full MNIST
training database (60, 000 digits) three times to the system.
Each input neuron is connected with one pixel of the image.
It emits spikes with a jittered rate that is proportional to
the pixel intensity (maximum rate is 22 Hz) as illustrated
in Figure 11(b). The initial phase is random. Input neurons
present spikes corresponding to a given digit during a period
of 350 ms, after which they present spikes corresponding to
another digit. No kind of preprocessing on the digits is used
and the set is not augmented with distortions. The network
is then tested on the MNIST test database, which consists in
10,000 digits that have not been presented during training.
Simulation time was about 8 hours per run on an AMD
Opteron 2216 CPU.
Figure 6 plots the synaptic conductances (or weights)
learned by the system in a configuration with only 10 output
neurons. It is remarkable that without any supervision and
using only our local custom STDP rule, the system has
identified 9 (out of 10) different numbers, the real features
of the input. Moreover it has learned the distinctive features
of the digits (and not just the most likely handwriting): it has
learnt the loop of the digit two, the bottom of the six, or the
horizontal parts of three and eight.
To evaluate the capability of the system, we can define a
recognition rate. For that purpose, we associate output neurons
with the digit for which they spike the most frequently a
posteriori, using a subset of 1000 well identified numbers.
In hardware this association could be performed with com-
plex digital circuitry. An alternative can be to associate the
unsupervised network with a supervised one [48]. All the
simulations were repeated ten times, and the recognition rate
given is averaged on the ten runs.
In order to evaluate quantitatively the network’s recognition
rate, Figure 7 plots the final recognition rate on the test
database. With ten output neurons the recognition rate reaches
60%. To improve the recognition rate, we can introduce
additional output neurons, in which case some output neurons
respond to different handwritings of the same digit. All the
output neurons respond to some kind of digits, as explained
in section II-B3. With 50 output neurons, the recognition
rate reaches 81%, and with 300 output neurons 93.5%. A
70
80
0 20 40 60 80 100
Rel. std. dispersion s/µ
of the device parameters (%)
Initial conductance
α
p
and a
m
α
p
, a
m
,
G
min
and G
max
Figure 8. Recognition rate on the MNIST testing set with different kinds of
nanodevice (synaptic) variability. All the simulations were repeated ten times,
the error bar is one standard deviation. All the simulations have homeostasis.
s/m=10% 25% 50% 100%
Figure 9. Conductance as a function of pulse number (plotted similarly to
Figure 5), for 100 devices with different relative standard dispersion
σ
/µ on
the parameters α
p
, α
m
(from left to right 10%, 25%, 50% and 100%).
traditional artificial neural network with back-propagation and
300 hidden neurons (obtained with the same number of
adjustable parameters) reaches 95% [28], which compares
to our rate of 93.5%. In the literature, the best algorithm
has a largely superior 99.7% recognition rate, but using 12
million adjustable parameters (vs. 235, 200 here) and a largely
augmented training set [49]. Though our numbers are clearly
more modest, the interest here is that the network is fully
unsupervised, with simple local learning rules, and variability
immunity as is seen in the next section.
Thanks to the unsupervised nature of learning, the com-
plicated “labeling” step does not need to be performed right
away. Lots of unknown data may be presented for training, and
the labeling can be performed from a limited subset of well
identified data. This is a strong advantage for many problems
involving natural data. In many cases, a lot of data is available,
but that was not classified, and the system can here perform
this analysis by itself.
III. VARIABILITY IMMUNITY
A. Synaptic variability
We now exploit our system-level simulations to analyze
the robustness of our approach. We first study the impact of
nanodevices (synaptic) variability on the recognition rate of
the network. For this study, we simulated the network with
50 output neurons, introducing different kinds of variability.
Results are reported in Figure 8.
In the top curve of Figure 8, we evaluate the impact of vari-
ability of the initial conductance (i.e. the initial conductance of
the nanodevices, before learning starts). We can see it has no
![Figure 5. Evolution of the conductance for the devices from [13], fitted with equations 1 and 2. (a) device conductance (measured at 1V ) after each pulse in a serie of potentiating (V = −3.2V ) pulses. (b) same with depressing (V = 2.8V ) pulses. Diamond: experimental data, reproduced from [13]. Full line: equations 1 and 2.](/figures/figure-5-evolution-of-the-conductance-for-the-devices-from-bca6sxfn.webp)
