Impact of a Pocket Doping on the Device Performance of a Schottky Tunneling Field-Effect Transistor
TL;DR: In this article, the impact of using a pocket either at the source end or at both the source and the drain ends of a Schottky barrier tunneling FET (SB-TFET) was investigated.
Abstract: It is known that a pocket at the drain end of a Schottky barrier tunneling FET (SB-TFET) helps to improve the device performance in terms of greatly suppressed ambipolar current and reduced drain-induced barrier lowering (DIBL) A detailed investigation, with the help of a numerical device simulator, of the impact of using such a pocket either at the source end or at both the source and the drain ends of an SB-TFET is reported for the first time in this paper The performance of the above-mentioned two devices is compared with a device having a pocket at the drain end and a conventional MOSFET Optimization of the barrier height and the pocket parameters is made before performance comparison It is observed that a pocket at the drain end helps suppress the ambipolar current and reduce both the subthreshold swing and the DIBL On the other hand, a pocket at the source end helps to improve the ON-state current \(I_{\mathrm{{\scriptstyle ON}}}\) Using a pocket at both the source and the drain ends results in overall improvement of the device performance The effects of scaling on such device performance parameters are also reported
Citations
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TL;DR: In this paper, the authors addressed the issue of low ON current in a Schottky barrier (SB) MOSFET by proposing a novel structure of SB MOSFLET on silicon on insulator.
Abstract: In this paper, we address an important issue of low ON current in a Schottky barrier (SB) MOSFET by proposing a novel structure of Schottky MOSFET on silicon on insulator. The proposed Schottky device employs a dual material at the source side and is being named as the source engineered SB MOSFET (SE-SB-MOSFET). Erbium silicide (ErSi1.7) is used as the main source material, and Hafnium is used as a source extension. The use of Hafnium as a source extension induces an n+-type charge plasma in an undoped silicon film, which significantly reduces the SB thickness. A calibrated simulation study has shown that the ON current ( $I_{{{\mathrm{{\scriptscriptstyle ON}}}}}$ ) and $I_{{{\mathrm{{\scriptscriptstyle ON}}}}}/I_{{{\mathrm{{\scriptscriptstyle OFF}}}}}$ have increased by 225 and $65\times $ , respectively, in the proposed device in comparison with the conventional SB-MOSFET device. The ac analysis has shown that the cutoff frequency ( $f_{T}$ ) in the proposed SE-SB-MOSFET ( $\sim 200$ GHz) has increased by $200\times $ as compared with the conventional SB-MOSFET ( $\sim 1$ GHz). Furthermore, the performance of the proposed device has been tested at the circuit level also. It has been observed from the transient analysis that a significant reduction in switching ON delay ( $65\times $ ) and switching OFF delay (33%) has been achieved in the proposed SE-SB-MOSFET-based inverter in comparison with the conventional device-based inverter. Furthermore, the use of the charge plasma concept makes the fabrication of the proposed device relatively easy as it uses low thermal budget.
53 citations
Cites methods from "Impact of a Pocket Doping on the De..."
...In model calibration, the device structure, its dimensions and other parameters, is kept the same as used in [26] and [27], for the generation of the simulation data....
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...Model calibration against the experimental data, as reported in [26] and [27]....
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...We calibrated our model with the experimental data as reported in [26] and [27]....
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TL;DR: The cyclic addition and removal of glucose is shown to successively enhance and recover fluorescence, demonstrating reversibility that serves as a prerequisite for continuous glucose monitoring.
Abstract: This study presents a reversible, mediatorless, near-infrared glucose sensor based on glucose oxidase-wrapped SWCNTs. A combination of fluorescence, absorption, and Raman spectroscopy measurements suggest a fluorescence enhancement mechanism based on localized enzymatic doping of SWCNT defect sites that does not rely on added mediators. The cyclic addition and removal of glucose is shown to enhance and recover fluorescence, demonstrating reversibility.
52 citations
TL;DR: In this paper, a process-variation resilient electrostatically-doped ferroelectric Schottky-barrier tunnel FET (ED-FE-SB-TFET) based on negative capacitance (NC) was investigated.
Abstract: This work investigates a process-variation resilient electrostatically-doped ferroelectric Schottky-barrier tunnel FET (ED-FE-SB-TFET) based on negative capacitance (NC). The key attributes of ED-FE-SB-TFET are perovskite ferroelectric (FE) gate stack-induced NC behavior and electrostatic doping to induce pockets at both source/drain and channel interfaces. The positive feedback among the electric dipoles in FE material leads to intrinsic voltage amplification and enhanced gate controllability, thus it facilitates faster switching transitions. The proposed ED-FE-SB-TFET endeavors to create a substantial reduction in the ambipolar current (
$$I_\mathrm{Amb}$$
), steep sub-threshold slope, paramount boost in drive current, lower drain-induced barrier-lowering, and enhanced scalability. It also obviates the need for metallurgical doping, hence ion-implantation or dopant segregation techniques employed for planar SB-TFETs pocket-doping are no longer required, and it also modifies effective Schottky barrier height and Schottky tunneling barrier width significantly to enhance the device behavior. It offers a simplified fabrication process, and it is highly resilient towards process variations, doping control issues, and random dopant fluctuations. Moreover, there is a reduced thermal budget that facilitates its fabrication on single crystal silicon-on-glass substrate realized by wafer scale epitaxial transfer. Results reveal its potential as strong candidate for next generation, scaled and low power applications.
30 citations
TL;DR: In this paper, a ferroelectric gate stack with highly doped pocket at the source/drain and channel interface was proposed and investigated for the first time, and the increased tunneling probability improved the device performance in terms of high ION, high IOFF ratio, reduced IAMB and low subthreshold swing.
28 citations
TL;DR: In this article, a gate dielectric engineered (DE) dopant segregated (DS) SBMOS structure was proposed to solve an important issue of low ON-state current in the nickel silicide (NiSi) metal source/drain Schottky barrier (SB) MOSFET (SBMOS).
Abstract: In this paper, to solve an important issue of low ON-state current in the nickel silicide (NiSi) metal source/drain Schottky barrier (SB) MOSFET (SBMOS), we have reported a novel dielectric engineered (DE) dopant segregated (DS) SBMOS structure using gate dielectric engineering. In a proposed device, we employ two different gate dielectric materials. The high-k gate dielectric is used at the source side and low-k gate dielectric at the drain side. Beneath the high-k gate dielectric, electron accumulation increases due to large gate dielectric capacitance density. As a result, reduction in depletion of source side dopant segregation layer further decreases the SB tunneling width for the electron injection. Consequently, improvement in ON-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) is obtained. In addition, the low-k gate dielectric and drain side dopant segregation layer increases the effective SB height and tunneling width for the hole injection. Thus, the OFF-state current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) is suppressed. The optimization of proposed device has been performed by modulating the length of high-k and the low-k gate dielectric. In addition, we have compared the performance of the proposed device in terms of ON to OFF current ratio $({I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}})$ , subthreshold swing (SS), transconductance $({g}_{ {m}})$ , transconductance generation factor $({g}_{ {m}}/{I}_{ {D}})$ , cut-off frequency $({f}_{ {T}})$ , and gain-bandwidth product $({f}_{ {A}})$ to the SBMOS, DS SBMOS, and DS SBMOS with the full high-k gate dielectric. Moreover, we have proposed the possible process flow for the DE DS SBMOS fabrication.
26 citations
Cites background or methods from "Impact of a Pocket Doping on the De..."
...The following are the common simulation parameters for the above-mentioned device structures [7]: silicon film thickness (Tsi) = 10 nm, gate oxide thickness (Tox) = 2 nm, and channel doping concentration (Nch) = 1 × 1015cm−3 and for the S/D contacts formation, NiSi having electron SBH of 0....
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...NiSi DS SBMOS is to use high-k gate dielectric [2], [7], [14], [18]....
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...In NiSi SBMOS, due to large SB height (SBH) at the source side, SB tunneling is a dominant carrier transport mechanism [2], [7]....
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...The use of this model has been widely accepted in the recent literature [7], [9], [24], [25]....
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References
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TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material
1,583 citations
"Impact of a Pocket Doping on the De..." refers background in this paper
...I. INTRODUCTION BECAUSE of their capability of reducing both the short-channel effects (SCEs) and the parasitic resistances in scaled devices, MOSFETs with Schottky-barrier source/drain (SB-MOSFETs) have been extensively investigated in the past [1]–[12]....
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...Using a pocket at both the source and the drain ends results in overall improvement of the device performance parameters except for ION at Lg 30 nm, where a conventional MOSFET is found to be better....
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...For Lg 30 nm, MOSFET is found to be better than all other devices....
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...The performance of the above-mentioned two devices are compared with a drain-pocket SB-TFET, as used in [21], as well as with a conventional MOSFET with similar dimensions....
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...We now compare the device performance between the three different SB-TFETs and a conventional MOSFET....
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TL;DR: How the structure of the nanotube is the key enabler of this particular one-dimensional tunneling effect is discussed, which is controlled here by the valence and conduction band edges in a bandpass-filter-like arrangement.
Abstract: A detailed study on the mechanism of band-to-band tunneling in carbon nanotube field-effect transistors (CNFETs) is presented. Through a dual-gated CNFET structure tunneling currents from the valence into the conduction band and vice versa can be enabled or disabled by changing the gate potential. Different from a conventional device where the Fermi distribution ultimately limits the gate voltage range for switching the device on or off, current flow is controlled here by the valence and conduction band edges in a bandpass-filter-like arrangement. We discuss how the structure of the nanotube is the key enabler of this particular one-dimensional tunneling effect.
846 citations
Proceedings Article•
01 Jun 2006TL;DR: Tunnel field effect transistors (TFETs) with record high I ON /I OFF ratio (≫106) for lowvoltage (0.5V) operation are achieved by using germanium in the source region to achieve a small tunnel bandgap.
Abstract: Tunnel field effect transistors (TFETs) with record high I ON /I OFF ratio (≫106) for low-voltage (0.5V) operation are achieved by using germanium in the source region to achieve a small tunnel bandgap. The measured data are well explained by the theoretical band-to-band tunneling current model. Using the calibrated analytical model, the energy-delay performance of TFET-based technology is compared against that of conventional CMOS technology, at the 65nm node. The TFET is projected to provide dramatic improvement in energy efficiency for performance in the range up to ∼0.5GHz.
283 citations
01 Dec 2008
TL;DR: In this article, the Drift Tunnel FET (DTFET) was proposed to solve the TFET bipolar parasitic conduction by a novel TFET architecture, with improved OFF state control, and demonstrated functional TFET and CMOS devices on Si1-xGexOI (x=15-30-100%) co-integrated with the same SOI process flow.
Abstract: We report for the first time experimental investigations on SOI, Si1-xGexOI & GeOI Tunnel FET (TFET). These devices were fabricated using a Fully Depleted SOI CMOS process flow with high k-metal gate stack, enabling 2 decades lower IOFF (~30fA/mum) compared to co-processed CMOS. We successfully solve the TFET bipolar parasitic conduction by a novel TFET architecture, the Drift Tunnel FET (DTFET), with improved OFF state control. Concerning the ON current issue, we improve the SOI p (resp. n) TFET ION by a factor 55 (resp. 8) by source-drain profiles optimization (via spacers & extensions). Moreover, we demonstrate for the first time functional TFET & CMOS devices on Si1-xGexOI (x=15-30-100%) co-integrated with the same SOI process flow, enabling TFET ION continuous improvement with Ge content increase: ION x2700 for GeOI (compared to SOI).
282 citations
15 Jun 2010
TL;DR: In this paper, a novel tunneling field effect transistor (TFET) fabricated with a high-k/metal gate stack and using nickel silicide to create a special field-enhancing geometry and a high dopant density by dopant segregation was reported.
Abstract: We report a novel tunneling field effect transistor (TFET) fabricated with a high-k/metal gate stack and using nickel silicide to create a special field-enhancing geometry and a high dopant density by dopant segregation It produces steep subthreshold swing (SS) of 46mV/dec and high I ON /I OFF ratio (∼108) and the experiment was successfully repeated after two months Its superior operation is explained through simulation For the first time convincing statistical evidence of sub-60mV/dec SS is presented More than 30% of the devices show sub-60mV/dec SS after systemic data quality checks that screen out unreliable data
199 citations
"Impact of a Pocket Doping on the De..." refers background in this paper
...A metal silicide having a relatively large barrier height in place of the doped semiconductor in the source region of a TFET has also been proposed in the recent past [20]–[22]....
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