Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor

Abstract: In this paper, we have investigated device reliability by studying the impact of interface traps, both donor (positive interface charges) and acceptor (negative interface charges), present at the Si/SiO2 interface, on analog/RF performance and linearity distortion analysis of heterogeneous-gate-dielectric gate-all-around tunnel FET (HD-GAA-TFET), which is used to enhance the tunneling current of TFET. Various figures of merit such as cutoff frequency $f_{{T}}$ , maximum oscillation frequency $f_{\max}$ , transconductance frequency product, higher order transconductance coefficients $({g}_{{m}1}, {g}_{{m}3})$ , VIP2, VIP3, IIP3, IMD3, zero crossover point, and 1-dB compression point have been investigated, and the results obtained are simultaneously compared with a gate-all-around TFET (GAA-TFET). Simulation results indicate that HD-GAA-TFET is more immune toward the interface trap charges present at the Si/SiO2 interface than the GAA TFET and hence can act as a better candidate for low power switching applications. All simulations have been done on an ATLAS device simulator.

Abstract: In this paper, the analog performance is reported for the first time for a double-gate (DG) n-type tunnel field-effect transistor (n-TFET) with a relatively small body thickness (10 nm), which shows good drain current saturation. The device parameters for analog applications, such as transconductance gm, transconductance-to-drive current ratio gm/ID, drain resistance RO, intrinsic gain, and unity-gain cutoff frequency fT, are studied for DG n-TFET, with the help of a device simulator, and compared with that for a similar DG n-MOSFET. Although gm is lower, gm/ID is found to be higher in TFET, except for small values of the gate overdrive voltage, indicating that a TFET can produce higher gain at the same power level than a MOSFET. An extremely high RO and, hence, a high intrinsic gain are also observed for a TFET as compared with that for a MOSFET. A complementary TFET amplifier is found to have more than one order of magnitude higher voltage gain than its MOS counterpart. It is also demonstrated that the drain resistance and, hence, the device gain significantly degrade for increasing body thickness of a TFET.

Abstract: Because of its different current injection mechanism, a tunnel field-effect transistor (TFET) can achieve a sub-60-m/decade subthreshold swing at room temperature, which makes it very attractive in replacing a metal-oxide semiconductor field-effect transistor, particularly for low-power applications It is well known that some specific TFET structures show a good drain current ID saturation in the output characteristics, whereas other structures do not A detailed investigation, through extensive device simulations, of the role of the channel on the drain-potential dependence of double-gate TFET characteristics is presented in this paper for the first time It is found that a good saturation of ID is observed only for devices in which a thin silicon body is used A relatively thick silicon body or gate-drain underlaps result in the penetration of the drain electric field through the channel, which does not allow the drain current to saturate, even at higher drain voltages

Abstract: In this paper, a short-gate tunneling-field-effect-transistor (SG-TFET) structure has been investigated for the dielectrically modulated biosensing applications in comparison with a full-gate tunneling-field-effect-transistor structure of similar dimensions. This paper explores the underlying physics of these architectures and estimates their comparative sensing performance. The sensing performance has been evaluated for both the charged and charge-neutral biomolecules using extensive device-level simulation, and the effects of the biomolecule dielectric constant and charge density are also studied. In SG-TFET architecture, the reduction of the gate length enhances its drain control over the band-to-band tunneling process and this has been exploited for the detection, resulting to superior drain current sensitivity for biomolecule conjugation. The gate and drain biasing conditions show dominant impact on the sensitivity enhancement in the short-gate biosensors. Therefore, the gate and drain bias are identified as the effective design parameters for the efficiency optimization.

Abstract: The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in this study are drain current (I D ), ON-state to OFF-state current ratio (I ON /I OFF ), subthreshold slope (SS), drain induced barrier lowering (DIBL), intrinsic gain (G m R O ), output conductance (G D ), transconductance/drain current ratio (G m /I D ) and unity gain cut-off frequency (f T ). The effects of varying the spacer dielectric constant (k sp ) on the electrical characteristics of the device are studied. It is observed that the use of a high-k dielectric as a spacer brings an improvement in the OFF-state current by more than one order of magnitude thereby making the device more scalable. However, the ON-state current is only marginally affected by increasing dielectric constant of spacer. The effects of spacer width (W sp ) on device performance are also studied. ON-state current marginally decreases with spacer width.

Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material

Abstract: In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.

Abstract: The Zener current in a constant field is calculated both with and without the W annier -A dams reduction of the interband-coupling terms. The Zener current is only slightly different in the two cases, a fact which has already been noted by W annier . The apparent reduction of interband coupling is interpreted as a polarization correction. A detailed calculation of the Zener current is made for a simple two-band model which is applicable to InSb. The evaluation of the tunneling integral follows closely a calculation due to K eldysh .

Abstract: The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a “tunneling epoch”, in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.

Abstract: A silicon surface tunneling transistor structure, based on lateral band‐to‐band tunneling, is presented The theory, fabrication, and operation of the device is described Band‐to‐band tunneling is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier The operation of the device is confirmed in both experimental results and two‐dimensional computer simulations Dramatic differences in drain current are observed for different gate bias