Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor
TL;DR: In this paper, the effects of varying the dielectric constant and width of the spacer are studied, and it is observed that the use of a low-dielectric as a spacer causes an improvement in its on-state current.
Abstract: A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low- dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (~30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate-source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high- spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it.
Citations
More filters
TL;DR: In this article, an underlap silicon n-channel tunnel field effect transistor (n-TFET) with symmetric single-k spacer (SSS) double gate NTFET is proposed to improve the performance of the device by using different spacer materials.
11 citations
04 Jun 2013
TL;DR: In this article, the authors investigated the deteriorating effect of source voltage on the performance of N-type vertical tunnel FETs and proposed a double gate vertical tunnel structure as a solution to this problem.
Abstract: We investigate the deteriorating effect of source voltage on the performance of N-type vertical tunnel FETs. A non-zero source voltage may appear due to series connection of FETs. Theoretical analysis, backed with TCAD simulation, highlights the role of source voltage in undesired band bending and consequent change in various electrical parameters. We propose a double gate vertical tunnel FET structure as a solution to this problem. Such a structure nullifies any undesired bending in energy bands due to source voltage. Further, we utilize the proposed TFET to design hybrid CMOS-TFET based low standby power logic circuits; where the intrinsic properties of tunnel FET ensures the reduction of standby mode leakage current and supply voltage, while the modified tunnel FET enables the series connection of FETs. The proposed hybrid circuit utilizes minimum number of N-type tunnel FETs and hence minimizes the need for advanced and susceptible process steps associated with vertical tunnel FETs. Compared with conventional low standby power circuits, the hybrid combination shows four orders of reduction in sleep mode leakage current.
11 citations
Cites background from "Impact of a Spacer Dielectric and a..."
...Other tunneling suppression techniques like gate overlap [6] and heterojunctions employing high band gap material in nontunneling regions [7] can also be used as an alternative to oxide....
[...]
06 Mar 2014
TL;DR: In this paper, the effect of Germanium mole fraction variation in the source region of a dielectrically modulated Silicon Tunneling Field Effect Transistor (DMTFET) based biosensor has been investigated with the help of extensive device-level simulation.
Abstract: In this work, the effect of Germanium mole fraction variation in the source region of a dielectrically modulated Silicon Tunneling Field Effect Transistor (DMTFET) based biosensor has been investigated with the help of extensive device-level simulation. Results show that the increasing germanium mole fraction significantly reduces the DMTFET sensitivity towards the bio-molecules, and the degree of this sensitivity degradation has strong dependence on the properties of bio-molecule namely dielectric constant and charge density. The increasing Germanium mole fraction reduces the effect of gate fringing field at the source region and consequently the conduction band lowering being diminished in this region, resulting in the sensitivity degradation in the DMTFET biosensor. This study offers a fair design level understanding over the use of Silicon-Germanium source in DMTFET based biosensor.
11 citations
Cites background or result from "Impact of a Spacer Dielectric and a..."
...This observation is in sync with the reported results on gate dielectric constant variation in TFET [16-19]....
[...]
...In accordance with reported literatures on gate dielectric constant variation in TFET [16-19], the gate induced fringing field effect over source region can be identified as the key contributing factor for conduction band lowering at the source side of tunneling junction of DMTFET....
[...]
TL;DR: In this paper, the authors investigated a source pocket tunnel field effect transistor (SP TFET) with dual work function of single gate material by using uniform and Gaussian doping profile in the drain region for ultra-low power high frequency high speed applications.
Abstract: We investigate a systematic study of source pocket tunnel field-effect transistor (SP TFET) with dual work function of single gate material by using uniform and Gaussian doping profile in the drain region for ultra-low power high frequency high speed applications. For this, a n+ doped region is created near the source/channel junction to decrease the depletion width results in improvement of ON-state current. However, the dual work function of the double gate is used for enhancement of the device performance in terms of DC and analog/RF parameters. Further, to improve the high frequency performance of the device, Gaussian doping profile is considered in the drain region with different characteristic lengths which decreases the gate to drain capacitance and leads to drastic improvement in analog/RF figures of merit. Furthermore, the optimisation is performed with different concentrations for uniform and Gaussian drain doping profile and for various sectional length of lower work function of the gat...
10 citations
Additional excerpts
...…2017 Informa UK Limited, trading as Taylor & Francis Group κ-spacer, and source pocket (Bhuwalka, Schulze, & Eisele, 2005; Boucart & Ionescu, 2007; Chattopadhyay & Mallik, 2011; H-Toh, Wang, Samudra, & Yeo, 2007; Ionescu & Riel, 2011; Kim, Kam, & Liu, 2009; Poon, Yau, Johnston, & Beecham,…...
[...]
TL;DR: In this paper, a dual dielectric constant spacer source/drain, overlapped double gate tunnel FET with a source pocket was investigated using two-dimensional Technology Computer-Aided Design (TCAD) device simulator.
Abstract: Impact of interface trap charges (ITCs) as well as temperature on the performance of a proposed dual dielectric constant spacer source/drain, overlapped double gate tunnel FET with a source pocket was investigated using two-dimensional Technology Computer-Aided Design (TCAD) device simulator. The proposed device is Si-based with Germanium as the source material, SiGe as a pocket material, and has a high-k gate dielectric. Its performance in terms of DC and analog/RF parameters vis-a-vis a conventional double gate PNPN TFET was compared. The device shows better results than the conventional one with an ON current of 1.71 × 10−3 A/µm, ON–OFF current ratio 1011, and subthreshold swing of 45 mV/decade. The study was focused on the analysis of the electric field, transfer characteristics, transconductance (gm), output conductance (gd), parasitic capacitances, gain-bandwidth product (GBP), cut off frequency (fT) for both the damaged (presence of donor/acceptor interface trap charges) and undamaged (no trap) conditions. The study revealed that the proposed structure is more immune to the interfacial trap charges as compared to the conventional device. Apart from this, the analysis shows a degradation of subthreshold swing (SS) and OFF current (IOFF) at elevated temperatures.
10 citations
References
More filters
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material
1,583 citations
"Impact of a Spacer Dielectric and a..." refers background in this paper
...Both the theoretical and experimental results show that S can be much lower than 60 mV/dec for a TFET [6]–[8]....
[...]
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Abstract: In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.
1,230 citations
TL;DR: In this paper, the Zener current in a constant field is calculated both with and without the W annier -A dams reduction of the interband-coupling terms, interpreted as a polarization correction.
847 citations
"Impact of a Spacer Dielectric and a..." refers background in this paper
...Again, the device current depends upon the tunnel width and the electric field across the tunneling junction [23], and this has...
[...]
TL;DR: In this paper, the complementary Si-based tunneling transistors are investigated in detail, and it is found that the band-to-band tunneling current is controlled by the gate-tosource voltage.
Abstract: The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a “tunneling epoch”, in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.
428 citations
TL;DR: A silicon surface tunneling transistor structure, based on lateral band-to-band tunneling, is presented in this article, which is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier.
Abstract: A silicon surface tunneling transistor structure, based on lateral band‐to‐band tunneling, is presented The theory, fabrication, and operation of the device is described Band‐to‐band tunneling is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier The operation of the device is confirmed in both experimental results and two‐dimensional computer simulations Dramatic differences in drain current are observed for different gate bias
347 citations
"Impact of a Spacer Dielectric and a..." refers background in this paper
...2101603 Moore’s law, the tunnel FET (TFET) shows great promise [1]–...
[...]