Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor
TL;DR: In this paper, the effects of varying the dielectric constant and width of the spacer are studied, and it is observed that the use of a low-dielectric as a spacer causes an improvement in its on-state current.
Abstract: A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low- dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (~30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate-source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high- spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it.
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TL;DR: In this article, the electrostatic behavior of the different configurations of n-type heterojunction double-gate tunnel field effect transistor (HDGTFET) has been analyzed based on the basics of the circuit elements such as drain current, transconductance, parasitic capacitances, cutoff frequency and gain bandwidth product.
Abstract: The electrostatic behaviour of the different configurations of n-type heterojunction double-gate tunnel field-effect transistor (HDGTFET) has been analysed. The analysis is based on the basics of the circuit elements such as drain current, transconductance, parasitic capacitances, cut-off frequency and gain bandwidth product. From the investigation carried out, it can be inferred that dual metal hetero-dielectric double-gate HDGTFET with gate underlap achieves both low standby power OFF state current and high performance at low supply voltage. The performance of the device having different configurations has been analysed for drain region having a uniform and Gaussian doping profile.
4 citations
Cites background from "Impact of a Spacer Dielectric and a..."
...channel–drain junction and also, it reduces gate-to-drain parasitic capacitance as the gate moves away from the drain [16, 17]....
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TL;DR: In this article, the authors reported a new phenomenon in double-gate silicon TFETs, which causes a sudden increase in drain current at larger drain voltages, independent of whether they show a good output current saturation in the initial portion of their output characteristics.
Abstract: It is well-established that a tunnel field-effect transistor (TFET) may or may not show a good drain current saturation in its output characteristics, depending upon its device structure. In this paper, we report for the first time a new phenomenon in double-gate silicon TFETs, which causes a sudden increase in its drain current at larger drain voltages, independent of whether they show a good output current saturation or not in the initial portion of their output characteristics. It is observed that larger drain voltages result in band-to-band tunneling of the electrons occurring from the valance band of the channel to the conduction band of the drain, which causes such sudden increase of drain current.
3 citations
21 Feb 2013
TL;DR: In this paper, the authors studied the electrical characteristics of double-gated thin-body TFET with gate/source overlap and no abrupt source/channel junction from transfer characteristics, hump phenomenon occurring with increasing gate bias is observed.
Abstract: Most of research groups have studied on Tunneling Field-Effect Transistors (TFETs) with assumption that there are no gate/source overlap and abrupt source/channel junction In this work, we study the electrical characteristics of double-gated thin-body TFET with gate/source overlap and no abrupt source/channel junction From transfer characteristics, hump phenomenon occurring with increasing gate bias is observed This phenomenon affects the threshold voltage (VTH), which worsens device matching and also makes it difficult to design logic circuits The reason why tunneling current is suddenly increased is due to tunneling components in a direction normal to the channel Theses hump phenomena are not seen in the previous TFET study using unidirectional nonlocal band-to-band tunneling model
3 citations
TL;DR: In this paper, the performance of a sub-100nm gate-length p-channel TFET-based biosensor (pTFET-BS) covering a wide range of protein-molecules is presented.
Abstract: The performance of a sub-100-nm gate-length p-channel TFET-based biosensor (pTFET-BS) covering a wide range of protein-molecules is presented, and for the first time the optimized length-range of t...
3 citations
20 Apr 2017
TL;DR: In this paper, the effect of spacer-drain overlap on the performance of the double gate tunnel field effect transistor is investigated and compared with the single gate tunnel FET with spacer drain overlap using vertical tunneling concept.
Abstract: Effects of the spacer-drain overlap on the performance parameters of the double gate tunnel field effect transistor is proposed and investigated in this paper. By proper fabrication of the spacer-drain overlap, we can obtain a lower sub-threshold swing, smaller short channel effect (SCEs), i.e. drain induced barrier lowering (DIBL), higher ON-state current (ION) and considerably less OFF-state current (IOFF). Here we also measure effects of the channel length variation of the device. In this paper, we compare the proposed device with single gate tunnel FET with spacer-drain overlap using vertical tunneling concept. So we can observed, that the proposed device gives better performance parameters.
3 citations
Cites background from "Impact of a Spacer Dielectric and a..."
...Ge-GaAs heterojunction doping less TFET [9], gate overlap/underlap DGTFET with spacer [10],etc....
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References
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TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material
1,583 citations
"Impact of a Spacer Dielectric and a..." refers background in this paper
...Both the theoretical and experimental results show that S can be much lower than 60 mV/dec for a TFET [6]–[8]....
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TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Abstract: In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.
1,230 citations
TL;DR: In this paper, the Zener current in a constant field is calculated both with and without the W annier -A dams reduction of the interband-coupling terms, interpreted as a polarization correction.
847 citations
"Impact of a Spacer Dielectric and a..." refers background in this paper
...Again, the device current depends upon the tunnel width and the electric field across the tunneling junction [23], and this has...
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TL;DR: In this paper, the complementary Si-based tunneling transistors are investigated in detail, and it is found that the band-to-band tunneling current is controlled by the gate-tosource voltage.
Abstract: The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a “tunneling epoch”, in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.
428 citations
TL;DR: A silicon surface tunneling transistor structure, based on lateral band-to-band tunneling, is presented in this article, which is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier.
Abstract: A silicon surface tunneling transistor structure, based on lateral band‐to‐band tunneling, is presented The theory, fabrication, and operation of the device is described Band‐to‐band tunneling is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier The operation of the device is confirmed in both experimental results and two‐dimensional computer simulations Dramatic differences in drain current are observed for different gate bias
347 citations
"Impact of a Spacer Dielectric and a..." refers background in this paper
...2101603 Moore’s law, the tunnel FET (TFET) shows great promise [1]–...
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