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Journal ArticleDOI

Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor

22 Feb 2011-IEEE Transactions on Electron Devices (IEEE)-Vol. 58, Iss: 3, pp 677-683
TL;DR: In this paper, the effects of varying the dielectric constant and width of the spacer are studied, and it is observed that the use of a low-dielectric as a spacer causes an improvement in its on-state current.
Abstract: A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low- dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (~30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate-source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high- spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it.
Citations
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Proceedings ArticleDOI
01 Jun 2015
TL;DR: In this article, a PAC-TFET with double gate geometry has been proposed to control the polarity and ambipolar current conduction simultaneously, and two independently driven gates provide the opportunity to configure the n-type or p-type operation of TFET along with an additional control to suppress AM conduction.
Abstract: Ambipolar conduction in Tunnel Field Effect Transistor (TFET) is a major challenge which limits its applications for energy efficient logic circuit designs. In this work a new device architecture i.e. PAC-TFET with Double Gate geometry has been proposed to control the polarity and ambipolar current conduction simultaneously. Two independently driven gates provide the opportunity to configure the polarity of TFET (n-type or p-type device operation) along with an additional control to suppress ambipolar current conduction.

3 citations

Book ChapterDOI
04 Jul 2019
TL;DR: The implemented spiking neural network circuit has been implemented by using 3D tunneling device based on SiGe as a source for circuit applications and has a quick response and efficient spiking pulse train with negligible leakage current.
Abstract: In this paper, the spiking neural network has been implemented by using 3D tunneling device based on SiGe as a source for circuit applications. Here, Device circuit co-design investigations have been made in terms of device characteristics and circuit parameters using Synopsys 3D TCAD software and HSPICE simulation. The implemented circuit minimizes the spiking time with the help of tunneling transistors. The proposed tunneling device use the merits of low band gap material such as SiGe, used as a material in the source region with low spacer width, reduces the depletion of the fringing field over source gate edge, leads to high (\(I_{ON}\)). Whereas, drain underlap increases the drain channel resistance, and significantly reduces leakage current (\(I_{OFF}\)). The spiking neural network circuit has been simulated by applying the test signal at the excitatory input to the benchmark circuit and observe the output response at the inhibitory node, it has a quick response and efficient spiking pulse train with negligible leakage current.

3 citations

Journal ArticleDOI
30 Jun 2014
TL;DR: In this paper, the impact of various parameter variations on the performance of a DG-PNIN tunnel field effect transistor is investigated and all these parameters are optimized as performance boosters to give better current characteristics parameters.
Abstract: The downscaling of conventional MOSFETs has come to its fundamental limits. TFETs are very attractive devices for low power applications because of their low off-current and potential for smaller sub threshold slope. In this paper, the impact of various parameter variations on the performance of a DG-PNIN Tunnel field effect transistor is investigated. In this work, variations in gate oxide material, source doping, channel doping, drain doping, pocket doping and body thickness are studied and all these parameters are optimized as performance boosters to give better current characteristics parameters. After optimization with all these performance boosters, the device has shown improved performance with increased on-current and reduced threshold voltage and the Ion/Ioff ratio is > 10 6 .

2 citations


Cites background from "Impact of a Spacer Dielectric and a..."

  • ...Due to their low sub threshold swing (SS<60mv/dec), less susceptibility to short channel effects (SCEs), very low leakage current, Tunnel Field Effect Transistor (TFET) has been considered as an alternative for low power CMOS applications[4-12]....

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Journal ArticleDOI
TL;DR: In this paper, the effects of dielectric materials for spacers on the performance characteristics of germanium-based tunneling field effect transistors (TFETs) were investigated.
Abstract: In this study, we investigated the effects of dielectric materials for spacers on the performance characteristics of germanium (Ge)-based tunneling field-effect transistors (TFETs). Direct current (DC), radio frequency (RF), and switching performance characteristics were analyzed using various spacer dielectric materials including recent interlayer dielectric (ILD) oxides, silicon dioxide (SiO2), silicon nitride (Si3N4), and hafnium oxide (HfO2). Since spacer dielectrics affect the band bending in the source and drain regions caused by fringing fields, a Ge-based TFET having a low-κ spacer dielectric showed a high current drivability owing to its steep energy-band bending on the source side. At the same time, outstanding switching and RF performance characteristics were achieved by reducing parasitic capacitances when a low-κ spacer dielectric was employed. On this basis, a Ge-based TFET with a low-κ spacer dielectric was designed with a drain underlap for satisfactory control of the ambipolar behaviors and for optimization of RF performance characteristics. It was proven that the drain underlap suppressed ambipolar current characteristics and reduced gate capacitance by minimizing the electric field induced by the gate electrode on the drain-side channel without degradation of current drivability.

2 citations

References
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Journal ArticleDOI
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material

1,583 citations


"Impact of a Spacer Dielectric and a..." refers background in this paper

  • ...Both the theoretical and experimental results show that S can be much lower than 60 mV/dec for a TFET [6]–[8]....

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Journal ArticleDOI
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Abstract: In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.

1,230 citations

Journal ArticleDOI
Evan O. Kane1
TL;DR: In this paper, the Zener current in a constant field is calculated both with and without the W annier -A dams reduction of the interband-coupling terms, interpreted as a polarization correction.

847 citations


"Impact of a Spacer Dielectric and a..." refers background in this paper

  • ...Again, the device current depends upon the tunnel width and the electric field across the tunneling junction [23], and this has...

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Journal ArticleDOI
TL;DR: In this paper, the complementary Si-based tunneling transistors are investigated in detail, and it is found that the band-to-band tunneling current is controlled by the gate-tosource voltage.
Abstract: The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a “tunneling epoch”, in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.

428 citations

Journal ArticleDOI
TL;DR: A silicon surface tunneling transistor structure, based on lateral band-to-band tunneling, is presented in this article, which is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier.
Abstract: A silicon surface tunneling transistor structure, based on lateral band‐to‐band tunneling, is presented The theory, fabrication, and operation of the device is described Band‐to‐band tunneling is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier The operation of the device is confirmed in both experimental results and two‐dimensional computer simulations Dramatic differences in drain current are observed for different gate bias

347 citations


"Impact of a Spacer Dielectric and a..." refers background in this paper

  • ...2101603 Moore’s law, the tunnel FET (TFET) shows great promise [1]–...

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