Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor
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Cites background from "Impact of a Spacer Dielectric and a..."
...The spacer is assumed to be air with a dielectric constant of 1 to reduce the fringing field’s impact [54]....
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Cites background from "Impact of a Spacer Dielectric and a..."
...In order to address the problems, some of the approaches taken are by introducing thinner spacer with higher values [3],[4] and by introducing a gate stack (GS) configuration i....
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Cites background from "Impact of a Spacer Dielectric and a..."
...Avik Chattopadhyay and Abhijit Mallick proposed an impact of a spacer dielectric and a gate overlap/underlap on the TFET device performance in 2011 [10]....
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References
1,583 citations
"Impact of a Spacer Dielectric and a..." refers background in this paper
...Both the theoretical and experimental results show that S can be much lower than 60 mV/dec for a TFET [6]–[8]....
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847 citations
"Impact of a Spacer Dielectric and a..." refers background in this paper
...Again, the device current depends upon the tunnel width and the electric field across the tunneling junction [23], and this has...
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"Impact of a Spacer Dielectric and a..." refers background in this paper
...2101603 Moore’s law, the tunnel FET (TFET) shows great promise [1]–...
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