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Journal ArticleDOI

Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor

22 Feb 2011-IEEE Transactions on Electron Devices (IEEE)-Vol. 58, Iss: 3, pp 677-683
TL;DR: In this paper, the effects of varying the dielectric constant and width of the spacer are studied, and it is observed that the use of a low-dielectric as a spacer causes an improvement in its on-state current.
Abstract: A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low- dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (~30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate-source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high- spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it.
Citations
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Posted Content
TL;DR: In this paper, a triple heterojunction (THJ) TFET was proposed to resolve the low ON-current challenge of TFETs, and the doping profile of THJ-TFET was engineered to boost the resonant tunneling efficiency.
Abstract: Triple heterojunction (THJ) TFETs have been proposed to resolve the low ON-current challenge of TFETs. However, the design space for THJ-TFETs is limited by fabrication challenges with respect to device dimensions and material interfaces. This work shows that the original THJ-TFET design with 12 nm body thickness has poor performance, because its sub-threshold swing is 50 mV/dec and the ON-current is only 6 $\mu A/\mu m$. To improve the performance, the doping profile of THJ-TFET is engineered to boost the resonant tunneling efficiency. The proposed THJ-TFET design shows a sub-threshold swing of 40 mV/dec over four orders of drain current and an ON-current of 325 uA/um with VGS = 0.3 V. Since THJ-TFETs have multiple quantum wells and material interfaces in the tunneling junction, quantum transport simulations in such devices are complicated. State-of-the-art mode-space quantum transport simulation, including the effect of thermalization and scattering, is employed in this work to optimize THJ-TFET design.

1 citations


Cites background from "Impact of a Spacer Dielectric and a..."

  • ...The spacer is assumed to be air with a dielectric constant of 1 to reduce the fringing field’s impact [54]....

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Proceedings ArticleDOI
01 Aug 2015
TL;DR: In this article, the impact of using different gate dielectric materials (HfO2 and Si3N4) compared to the conventional SiO2 with equivalent oxide thickness (EOT) of 1.2 nm on the digital and analog performance of UTBB SOI MOSFETs of 10 nm gate length with different ground plane (GP) structures under the double-gate operation-mode by numerical simulations.
Abstract: In this work, we investigate the impact of using different gate dielectric materials i.e HfO2 and Si3N4 as compared to the conventional SiO2 with equivalent oxide thickness (EOT) of 1.2 nm on the digital and analog performance of UTBB SOI MOSFETs of 10 nm gate length with different ground plane (GP) structures under the double-gate (DG) operation-mode by numerical simulations. It is found that Si3N4 provides good digital and analog performance in terms of lower DIBL and higher voltage gain, Av. Meanwhile, GP-A structure which employed p+ doping under the source and drain regions beneath the BOX is able to provide not only high Av but also a stable gain throughout the frequency range as compared to other GP structures. Thus, the configuration of GP-A structure with Si3N4 as the high-k materials is proposed for the design of analog and RF circuits.

1 citations


Cites background from "Impact of a Spacer Dielectric and a..."

  • ...In order to address the problems, some of the approaches taken are by introducing thinner spacer with higher values [3],[4] and by introducing a gate stack (GS) configuration i....

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Journal ArticleDOI
TL;DR: In this paper , the authors investigated the impact of ferroelectricity of high-κ spacers on the electrical performance of Line-TFETs by numerical simulation using Technology Computer-Aided Design (TCAD).
Abstract: In this work, we have investigated the impact of ferroelectricity of high-κ spacers on the electrical performance of Line-TFETs (L-TFET) by numerical simulation using Technology Computer-Aided Design (TCAD). We observed that the ferroelectric spacer increases the fringing electric field near the tunneling cross-section at the source-epitaxial layer junction. This, in turn, increases the band-to-band tunneling (BTBT) generation and hence the drive capability of the device. Almost 2× improvement in the drive capability of L-TFET is observed when the saturation (P s ) and remanent polarization (P r ) of spacer material are kept at 60 μC/cm 2 and 3 μC/cm 2 , respectively, without any significant change in OFF current. A change of ~100 mV in the tunneling onset voltage is also observed, when P r is increased from 1 μC/cm 2 to 3 μC/cm 2 . A higher value of P r results in increasing I OFF due to the onset of BTBT at zero gate bias. A ~10 3 × increase in I OFF is noted when P r is increased beyond 3 μC/cm 2 . A change of 40 mV in the saturation voltage was also noted when P s is increased from 10 μC/cm 2 to 60 μC/cm 2 . We have also observed a significant change in the device’s transconductance (g m ) and output resistance (r o ) with the variation in ferroelectricity of the spacer material. The gate capacitances also change with P s and P r and hence the bandwidth.

1 citations

DOI
TL;DR: In this article , an asymmetric U-shaped-gated tunnel FET (AU-TFET), with a unique vertical channel epilayer, at sub-7-nm technology node, has been proposed and investigated for its suitability to be a universal device.
Abstract: In this article, for the first time, an asymmetric U-shaped-gated tunnel FET (AU-TFET), with a unique vertical channel epilayer, at sub-7-nm technology node, has been proposed and investigated for its suitability to be a universal device. After validating the simulation scheme with the experimental results of fabricated TFET devices, the impact of thickness of the said epilayer ( ${T}_{\text {epi}}$ ), on device performance, has been thoroughly investigated in terms of a variety of performance metrics, both in analog and digital (Ana–Digi) domains. To increase the vitality of the work, the device-level analysis is stretched to the circuit level. The impact on the inverter performance, both in Ana–Digi domains, in terms of fundamental circuit performance parameters, viz., dc gain, short-circuit power dissipation during switching, noise margin (NM), and so on, has been studied, and ultimately, the most optimized TFET structure, in each domain, has been identified. Finally, in this whole device/circuit co-analysis, after summing up all the performance metrics in both the domains while looking for meeting the low-power (LP) requirements (following the goals, as applicable, of international roadmaps), altogether, we have found that AU-TFET with ${T}_{\text {epi}} $ = 6 nm could be considered as the ultimate optimized universal LP Ana–Digi TFET structure.

1 citations

Proceedings ArticleDOI
01 Nov 2019
TL;DR: In this paper, a comparative study is performed between different gate source-drain overlap and gate channel underlap structures with conventional double gate tunnel field effect transistors (DGTFET) to overcome the challenges of scaling down of tunnel FET.
Abstract: In this work a comparative study is performed between different gate source-drain overlap and gate channel underlap structures with conventional double gate tunnel field effect transistors (DGTFET) to overcome the challenges of scaling down of tunnel FET. To attain better ON current (I ON ), band-to-band tunneling (BTBT) and subthreshold swing (SS), low energy band gap material (Ge) is used in heterojunction n-type DGTFET. All device combinations are incorporated with various $\kappa$ -values of dielectric spacer in order to investigate the best switching ratio keeping the leakage current (I OFF ) into consideration for low power applications. It is observed that for n-type gate underlap tunnel FET, a high- $\kappa$ spacer with minimum length of 5 nm underlap provides best device performance. However, for a given spacer a large gate channel underlap or a gate source-drain overlap relatively lowers the device performance. Subthreshold swing provided by the 5 nm gate channel underlap n-DGTFET is recorded best as 13.93 mV/decade of 50 nm gate length. It also results maximum drain current (I ON ) as $1.13\times 10^{-4}\ \ \mathrm{A}/\mu\mathrm{m}$ for different $\kappa$ -values of dielectric spacer at supply voltage (V DS ) of 0.5 V.

1 citations


Cites background from "Impact of a Spacer Dielectric and a..."

  • ...Avik Chattopadhyay and Abhijit Mallick proposed an impact of a spacer dielectric and a gate overlap/underlap on the TFET device performance in 2011 [10]....

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References
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Journal ArticleDOI
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material

1,583 citations


"Impact of a Spacer Dielectric and a..." refers background in this paper

  • ...Both the theoretical and experimental results show that S can be much lower than 60 mV/dec for a TFET [6]–[8]....

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Journal ArticleDOI
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Abstract: In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.

1,230 citations

Journal ArticleDOI
Evan O. Kane1
TL;DR: In this paper, the Zener current in a constant field is calculated both with and without the W annier -A dams reduction of the interband-coupling terms, interpreted as a polarization correction.

847 citations


"Impact of a Spacer Dielectric and a..." refers background in this paper

  • ...Again, the device current depends upon the tunnel width and the electric field across the tunneling junction [23], and this has...

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Journal ArticleDOI
TL;DR: In this paper, the complementary Si-based tunneling transistors are investigated in detail, and it is found that the band-to-band tunneling current is controlled by the gate-tosource voltage.
Abstract: The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a “tunneling epoch”, in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.

428 citations

Journal ArticleDOI
TL;DR: A silicon surface tunneling transistor structure, based on lateral band-to-band tunneling, is presented in this article, which is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier.
Abstract: A silicon surface tunneling transistor structure, based on lateral band‐to‐band tunneling, is presented The theory, fabrication, and operation of the device is described Band‐to‐band tunneling is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier The operation of the device is confirmed in both experimental results and two‐dimensional computer simulations Dramatic differences in drain current are observed for different gate bias

347 citations


"Impact of a Spacer Dielectric and a..." refers background in this paper

  • ...2101603 Moore’s law, the tunnel FET (TFET) shows great promise [1]–...

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