Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor
TL;DR: In this paper, the effects of varying the dielectric constant and width of the spacer are studied, and it is observed that the use of a low-dielectric as a spacer causes an improvement in its on-state current.
Abstract: A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low- dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (~30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate-source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high- spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it.
Citations
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TL;DR: In this paper, the effects of variation in temperature in the range of 300-450 K on the analog performance and harmonic distortion (HD) characteristics of a Ge-source tunnel FET (TFET) using a numerical device simulator were investigated.
Abstract: In this article, we report an investigation of the effects of variation in temperature in the range of 300–450 K on the analog performance and harmonic distortion (HD) characteristics of a Ge-source tunnel FET (TFET) using a numerical device simulator. Variation in the analog performance parameters, such as transconductance, intrinsic gain, and output resistance, is found to be small for such a large variation in temperature. HD parameters are also found to be almost insensitive to temperature variation over a good range.
21 citations
Cites methods from "Impact of a Spacer Dielectric and a..."
...Considerable efforts are being made worldwide to improve ION by various means such as using: 1) a low-bandgap material in the tunneling region [1]–[3]; 2) a double-gate architecture [2], [4]; 3) a high-k gate dielectric [4], [5]; 4) a low-k spacer [6]; 5) hetero gate dielectric [7]; 6) carrier tunneling in-line with gate field [8]–[11]; 7) innovative device architecture [10], [11]; 8) heterojunction [12]–[14], etc....
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01 May 2016
TL;DR: In this article, a study of DC and analog/RF response of dual work function hetero gate dielectric source pocket tunnel field effect transistor (DW HGD SP TFET) is presented, where source pocket is used to enhance the tunneling of charge carrier results in increment in ON-state current.
Abstract: This paper features a study of DC and analog/RF response of dual work function hetero gate dielectric source pocket tunnel field-effect transistor (DW HGD SP TFET). For this, source pocket is used to enhance the tunneling of charge carrier results in increment in ON-state current. Further, the hetero gate dielectric is used to reduce the gate to drain capacitance which is a crucial parameter for RF performance determination. At the same time, work function engineering is useful to enhance the device performance in terms of ON-state current which influences the analog/RF performance but it is also increases the gate to drain capacitance which limits the RF parameters. Thus, combination of hetero gate dielectric and work function engineering provides an integrated effect on the device RF performance. In this regards, RF parameters such as transconductance, cutoff frequency, gain bandwidth product and transit time are calculated to analysis the device suitability in wireless communication.
20 citations
Additional excerpts
...To solve these issue, various different approaches have been studied such as use of high-k material dielectric, use of band gap engineering, use of high density layer in the source side, and work function engineering to boost the ON-state current [4-13]....
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TL;DR: In this article, the effect of positive and negative interface trap charges on the dopingless device using charge plasma concept and named the proposed device as heterogeneous gate dielectric charge plasma tunnel field effect transistor (HD-CP-TFET).
Abstract: For the first time, we have explored the effect of positive and negative interface trap charges on the dopingless device using charge plasma concept and named the proposed device as heterogeneous gate dielectric charge plasma tunnel field-effect transistor (HD-CP-TFET). The heterogeneous gate dielectric is considered to improve the ON-state current and device performance. The main intention of this work is to improve the drain current, transconductance characteristics along with linearity figure-of-merits (FOMs). A comparative analysis is done with conventional CP-TFET in the presence of interface trap charges (ITCs). From comparative results, it is found that the proposed device shows a better performance in the presence of interface trap charges. All the simulations are performed on ATLAS TCAD device simulator. The results show that the proposed device has a better tunneling current, transconductance (
$$g_{\text {m}}$$
), cut-off frequency (
$$f_{\text {T}}$$
), second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third-order input intercept point (IIP3), and third-order intermodulation distortion (IMD3). Thus, the proposed device (HD-CP-TFET) shows the better performance in the presence of interface trap charges and indicates that this device is suitable for low-voltage analog/RF applications.
20 citations
TL;DR: In this article, the impacts of high-k gate dielectric permittivity on the device and circuit performances of a double-gate junctionless transistor (DGJLT) are studied with the help of extensive device simulations.
Abstract: The impacts of high-k gate dielectric permittivity on the device and circuit performances of a double-gate junctionless transistor (DGJLT) are studied with the help of extensive device simulations. The results are compared with a conventional inversion mode double-gate metal oxide semiconductor field effect transistor (DG MOSFET) of same dimension. Drain induced barrier lowering, intrinsic gain $$(G_{m}R_{O})$$(GmRO), and unity gain cut-off frequency $$(f_{T})$$(fT) are degraded with an increase in gate dielectric permittivity $$(k)$$(k). The transconductance $$(G_{m})$$(Gm) and gate capacitance $$(C_{GG})$$(CGG) are slightly affected with increase in $$k$$k. The gain of CMOS single stage amplifier and delay of inverter are found to be decreasing and increasing, respectively, with increase in $$k$$k. In order to mitigate these short channel effects due to the high-k gate dielectrics, a hetero-gate-dielectric structure with symmetric double-gate junctionless transistor (HG-DGJLT) is studied. HG-DGJLT offers superior $$G_{m}, \, C_{GG}$$Gm,CGG and $$f_{T}$$fT compared to $$\hbox {SiO}_{2}$$SiO2-only and $$\hbox {HfO}_{2}$$HfO2-only DGJLT. However, intrinsic gain of HG-DGJLT is inferior to $$\hbox {SiO}_{2}$$SiO2-only and $$\hbox {HfO}_{2}$$HfO2-only DGJLT.
20 citations
Abstract: In this paper, the analysis of SiGe source-based heterojunction Tunnel FET device is reported. The parameters like transconductance (gm), device efficiency (gm/ID), gate-source capacitance (CGS), gate-drain capacitance (CGD), cut-off frequency (fT), and gain-bandwidth product (GBP) are studied. DC, as well as AC simulations, have been performed on the proposed device. We have achieved an ON current of 0.537 mA/µm and an OFF current of 13 fA/µm, thus achieving ION/IOFF ratio as 3.72 × 1010. The values obtained for the transconductance are 0.68 milliSiemens, cut-off frequency is 446 GHz, gate-source capacitance is 0.387 femto Farads, and gate drain capacitance is 0.694 femtoFarads. The lower values of parasitic capacitances enable the device to be helpful for the low power and analog/RF applications even at high frequencies. The device has also been investigated for the temperature analysis concerning the drain current and the capacitance calculations. It was observed that the OFF currents are strongly dependent on the temperature in the drain current characteristics of the device. All the simulations have been performed on Visual TCAD (licensed version 1.9.2–3).
19 citations
References
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TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material
1,583 citations
"Impact of a Spacer Dielectric and a..." refers background in this paper
...Both the theoretical and experimental results show that S can be much lower than 60 mV/dec for a TFET [6]–[8]....
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TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Abstract: In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.
1,230 citations
TL;DR: In this paper, the Zener current in a constant field is calculated both with and without the W annier -A dams reduction of the interband-coupling terms, interpreted as a polarization correction.
847 citations
"Impact of a Spacer Dielectric and a..." refers background in this paper
...Again, the device current depends upon the tunnel width and the electric field across the tunneling junction [23], and this has...
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TL;DR: In this paper, the complementary Si-based tunneling transistors are investigated in detail, and it is found that the band-to-band tunneling current is controlled by the gate-tosource voltage.
Abstract: The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a “tunneling epoch”, in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.
428 citations
TL;DR: A silicon surface tunneling transistor structure, based on lateral band-to-band tunneling, is presented in this article, which is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier.
Abstract: A silicon surface tunneling transistor structure, based on lateral band‐to‐band tunneling, is presented The theory, fabrication, and operation of the device is described Band‐to‐band tunneling is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier The operation of the device is confirmed in both experimental results and two‐dimensional computer simulations Dramatic differences in drain current are observed for different gate bias
347 citations
"Impact of a Spacer Dielectric and a..." refers background in this paper
...2101603 Moore’s law, the tunnel FET (TFET) shows great promise [1]–...
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