Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor
TL;DR: In this paper, the effects of varying the dielectric constant and width of the spacer are studied, and it is observed that the use of a low-dielectric as a spacer causes an improvement in its on-state current.
Abstract: A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low- dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (~30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate-source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high- spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it.
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TL;DR: The outcomes reveal that the high fringing-field initiates for IGS < 10 nm and influences the tunneling probability and scattering strongly at 1-nm IGS, which affect the DC and RF characteristics; hence, optimized values of IGS are investigated and determined as IGS > 10 nm.
Abstract: Tunnel field-effect transistors (TFETs) are the decent performance estimators in the prospective of short-channel effects. In such structures, a small inter-gate separation (IGS) is a key factor that appraises for high packed-density with more number of channels ( $N$ ) to deliver superior performance. Hence, the investigation is majorly focused on scaling IGS and its fringing-field impact on device behavior for the first time. The outcomes reveal that the high fringing-field initiates for IGS 10 nm. The results state that the optimized IGS can provide source to deliver high ratio of on- and off-current ( $I_{on}/I_{off})$ . Even though, a small IGS is beneficial for reduction in the total capacitance, the RF performance improvement depends on a large IGS. The investigation is further extended and quantified for the finest IGS in multi-channel TFETs when $N$ varies from 1 to 10. These analyses are assessed for the emerging technological nodes.
13 citations
Cites background from "Impact of a Spacer Dielectric and a..."
...Furthermore, the absence of spacer in point-tunneling devices lead to increased field at channel-drain junction, implies high off-state current [40]....
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TL;DR: In this article, the influence of gate-drain underlap (UL) and different dielectric materials for the spacer and gate oxide on DG-TFET and its analog/RF performance for low power applications is investigated.
Abstract: The tunnel field effect transistor (TFET) and its analog/RF performance is being aggressively studied at device architecture level for low power SoC design. Therefore, in this paper we have investigated the influence of the gate-drain underlap (UL) and different dielectric materials for the spacer and gate oxide on DG-TFET (double gate TFET) and its analog/RF performance for low power applications. Here, it is found that the drive current behavior in DG-TFET with a UL feature while implementing dielectric material for the spacer is different in comparison to that of DG-FET. Further, hetero gate dielectric-based DG-TFET (HGDG-TFET) is more resistive against drain-induced barrier lowering (DIBL) as compared to DG-TFET with high-k (HK) gate dielectric. Along with that, as compared to DG-FET, this paper also analyses the attributes of UL and dielectric material on analog/RF performance of DG-TFET in terms of transconductance (gm ), transconductance generation factor (TGF), capacitance, intrinsic resistance (Rdcr), cut-off frequency (F T), and maximum oscillation frequency (F max). The LK spacer-based HGDG-TFET with a gate-drain UL has the potential to improve the RF performance of device.
13 citations
TL;DR: In this paper, a unique design for an asymmetrical underlap (AU) cylindrical-gate-all-around (GAA)-n-tunnel field effect transistor (TFET) based on hetero-spacer engineering with trap-assisted tunnelling (TAT) for reliability concern is proposed and validated.
Abstract: A unique design for an asymmetrical underlap (AU) cylindrical-gate-all-around (GAA)-n-tunnel field effect transistor (TFET) based on hetero-spacer engineering with trap-assisted tunnelling (TAT) for reliability concern is proposed and validated. Here, DC and analogue performances such as I ON, I OFF, SS, I ON /I OFF, C gs, and C gd have been investigated, while included TAT model and compared the examined device with AU GAA-TFET based on homo-spacer (HS) dielectric. On the basis of observation, the proposed device increases ON current as high as 2.1 × 10−6 A/µm, which corresponds to 1024 times improvement in I ON /I OFF when compared with device based on HS. It also suppresses ambipolar behaviour with fast switching ON–OFF transition due to low leakage current (I OFF). These performances are mainly produced due to AU and low-k spacer dielectric which is replaced by high-k dielectric over source side spacer of the device, whereas drain side spacer is placed with high-k material along with increase in series resistance across drain–channel junction caused by drain underlap. Low-k spacer reduces the fringing field, and the depletion does not form at the source–gate edge, hence high source–channel tunnelling junction.
12 citations
TL;DR: In this article, the authors investigated a method to suppress the ambipolar current Iamb effectively, enhance the device performance with higher on current Ion, lower off current Ioff, lower inverse subthreshold slope SS and simultaneously improve the RF performance.
Abstract: This paper investigates a method to suppress the ambipolar current Iamb effectively, enhance the device performance with higher on current Ion, lower off current Ioff, lower inverse subthreshold slope SS and simultaneously improve the RF performance. Starting with a conventional double-gate TFET structure, the device optimization reported in this work has led to the gradual improvement in device performance in terms of higher Ion, lower Ioff, higher Ion/Ioff ratio and lower SS. The RF parameters of the optimized GOTFET, such as the mutual transconductance gm, gate-to-drain CGD, and gate-to-source CGS capacitances and unity-gain cut-off frequency fT are analyzed. We have optimized the tunnel FET device using the industry-standard $\text {synopsys}^{{\circledR }}$
TCAD tools by studying the impact of various device parameters and dimensions on performance. We demonstrated that at high negative voltages, the proposed nGOTFET would completely suppress the ambipolar behavior of the device without deteriorating the device performance. We have compared the ambipolar current Iamb, Ioff, Ion, SS with 45 nm technology MOSFET and the TFETs reported earlier in literature. For the first time, we have proposed a GOTFET which completely suppresses the ambipolar current at high negative biases, without compromising the high Ion (1.04 mA/μ m) and low Ioff (0.27 pA/μ m) and low SS (32 mV/dec) at room temperature.
12 citations
Cites background from "Impact of a Spacer Dielectric and a..."
...Hence, researchers all over the world became interested in the TFET technology which replaces diffusion based minority carrier injection in conventional MOSFETs with quantum mechanical band-to-band (BtB) tunneling based minority carrier injection [3, 4]....
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TL;DR: The lower thermal requirements of a DL-DRAM opens the possibility of fabricating DRAMs using processes which are compatible with bio-materials and opto-electronics and in ensuring bottom MOSFET and interconnects preservation in 3D VLSI integration.
Abstract: In this paper, we have proposed a dopingless 1T DRAM (DL-DRAM) that utilizes the charge plasma concept. The proposed device employs a misaligned double-gate architecture to store holes and differentiates between the two logic states. The source, drain, backgate, and frontgate workfunctions are optimized to achieve the required concentration profiles in an intrinsic silicon body. Using TCAD simulations, we have analyzed the read/write mechanism in the device. Our study shows that the mechanism of current transport during reading operation depends strongly on the source workfunction. When the source workfunction is less than 4.5 eV the transport mechanism during reading is dominated by drift-diffusion. However, when the source workfunction is greater than 4.5 eV , the transport mechanism during read is dominated by band-to-band tunneling (BTBT). In general, when the dominant mechanism of current transport is BTBT, the retention time and the read-1/0 current ratio is higher, and the sense margin is lower in the case in which the dominant mechanism of current transport is drift-diffusion. Due to the avoidance of doping, the proposed DL-DRAM is expected to be free from random dopant fluctuation. Moreover, high temperature annealing processes required after ion implantation can be avoided. The lower thermal requirements of a DL-DRAM opens the possibility of fabricating DRAMs using processes which are compatible with bio-materials and opto-electronics and in ensuring bottom MOSFET and interconnects preservation in 3D VLSI integration.
11 citations
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TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material
1,583 citations
"Impact of a Spacer Dielectric and a..." refers background in this paper
...Both the theoretical and experimental results show that S can be much lower than 60 mV/dec for a TFET [6]–[8]....
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TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Abstract: In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.
1,230 citations
TL;DR: In this paper, the Zener current in a constant field is calculated both with and without the W annier -A dams reduction of the interband-coupling terms, interpreted as a polarization correction.
847 citations
"Impact of a Spacer Dielectric and a..." refers background in this paper
...Again, the device current depends upon the tunnel width and the electric field across the tunneling junction [23], and this has...
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TL;DR: In this paper, the complementary Si-based tunneling transistors are investigated in detail, and it is found that the band-to-band tunneling current is controlled by the gate-tosource voltage.
Abstract: The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a “tunneling epoch”, in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.
428 citations
TL;DR: A silicon surface tunneling transistor structure, based on lateral band-to-band tunneling, is presented in this article, which is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier.
Abstract: A silicon surface tunneling transistor structure, based on lateral band‐to‐band tunneling, is presented The theory, fabrication, and operation of the device is described Band‐to‐band tunneling is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier The operation of the device is confirmed in both experimental results and two‐dimensional computer simulations Dramatic differences in drain current are observed for different gate bias
347 citations
"Impact of a Spacer Dielectric and a..." refers background in this paper
...2101603 Moore’s law, the tunnel FET (TFET) shows great promise [1]–...
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