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Journal ArticleDOI

Impact of Different Barrier Layers and Indium Content of the Channel on the Analog Performance of InGaAs MOSFETs

18 Apr 2013-IEEE Transactions on Electron Devices (IEEE)-Vol. 60, Iss: 5, pp 1584-1589
TL;DR: In this article, a detailed investigation of the impact of different barrier layers on the analog performance of an InGaAs MOSFET is reported for the first time, and the device parameters for analog applications, such as transconductance (gm), transconductances-to-drive current ratio (gm/IDS), drain conductance (gd), intrinsic gain (m/gd), and unity-gain cutoff frequency (fT) are studied with the help of a device simulator.
Abstract: A barrier layer in an InGaAs MOSFET, which shows promise for high-performance logic applications due to enhanced electron mobility, is known to further improve the electron mobility. In this paper, a detailed investigation of the impact of different barrier layers on the analog performance of an InGaAs MOSFET is reported for the first time. The device parameters for analog applications, such as transconductance (gm), transconductance-to-drive current ratio (gm/IDS), drain conductance (gd), intrinsic gain (gm/gd), and unity-gain cutoff frequency (fT) are studied with the help of a device simulator. A barrier layer is found to improve the analog performance of such a device in general; with a double-barrier layer showing the best performance. An investigation on the impact of varying the indium content in the channel on the analog performance of an InGaAs MOSFET with a double-barrier layer is also reported in this paper. It is found that a higher In content results in better analog performance of such devices.
Citations
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Journal ArticleDOI
TL;DR: In this article, an extensive numerical analysis is performed to study and evaluate the impact of a dielectric sidewall spacer layer on the various device parameters associated with analog circuit performance of In0.75Ga0.25As channel asymmetric nMOSFETs with InP drain at two different channel lengths of 20 and 30 nm.
Abstract: An extensive numerical analysis is performed to study and evaluate the impact of a dielectric sidewall spacer layer on the various device parameters associated with analog circuit performance of In0.75Ga0.25As channel asymmetric nMOSFETs with InP drain at two different channel lengths ( $L_{g}$ ) of 20 and 30 nm. The numerical simulation deck is calibrated with asymmetric InGaAs MOSFET experimental characteristics reported in the literature. Our investigations reveal that device parameters such as transconductance $g_{m}$ , transconductance generation factor, and voltage gain $A_{v}$ exhibit significant improvement when a spacer of high dielectric constant $k$ , such as 25, and small length $L_{\textrm {sp}}$ , such as 5 nm, are used for both $L_{g}= 20$ and 30 nm. On the contrary, the output conductance and unity gain cutoff frequency are found to reduce and increase, respectively, with lower $k$ and larger $L_{\textrm {sp}}$ of the spacer. Our studies suggest that improved analog performance of In-rich asymmetric InGaAs MOSFETs can be achieved by spacer layer engineering at advanced technology nodes.

19 citations


Cites background from "Impact of Different Barrier Layers ..."

  • ...Effects of such strain are taken into account while computing the bandgap, and the conduction and valence band offsets of the channel [25], [26]....

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  • ...Earlier findings [24], [25] demonstrate that the effective electron mobility increases with increasing the In content in InGaAs....

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Journal ArticleDOI
TL;DR: In this article, the impact of channel material, channel thickness (T CH ), and gate length (L g ) on the various performance device metrics of Double-gate (DG) High Electron Mobility Transistor (HEMT) by using 2D Sentaurus TCAD simulation was analyzed.
Abstract: This work analyses the impact of channel material, channel thickness ( T CH ) and gate length ( L g ) on the various performance device metrics of Double-gate (DG) High Electron Mobility Transistor (HEMT) by using 2D Sentaurus TCAD simulation. A comparison between In 0.53 Ga 0.47 As/In 0.7 Ga 0.3 As/In 0.53 Ga 0.47 As sub-channel and In 0.7 Ga 0.3 As/InAs/In 0.7 Ga 0.3 As composite channel DG-HEMT along with SG-HEMT is made by characterizing the device with structural and geometrical parameters suitable for applications requiring high frequency operations. The DG-In 0.53 Ga 0.7 As/In 0.7 Ga 0.3 As/In 0.53 Ga 0.7 As sub-channel/DG-In 0.7 Ga 0.3 As/InAs/In 0.7 Ga 0.3 As composite channel HEMT with channel thickness of 13 nm and barrier thickness ( T B ) of 2 nm with L g = 30 nm are seen offering a positive threshold voltage ( V T ) of 0.298/0.21 V, transconductance ( g m ) of 3.09/3.3 mS/µm, with cut-off frequency ( f T ) and maximum oscillation frequency ( f max ) of 776/788 GHz and 905/978 GHz, respectively at V ds = 0.5 V is obtained. If the channel thickness of the DG-InAs composite channel device is scaled and reduced to 10 nm, the RF performances are further enhanced to 809 GHz ( f T ) and 1030 GHz ( f max ). Compared to DG-InGaAs sub-channel device, the device with thin DG-InAs composite channel device shows a better performance in terms of drain current ( I ds ), analog/RF performance thereby making it preferable for future THz applications.

17 citations

Journal ArticleDOI
TL;DR: Investigations reveal that the CMOS circuits comprising of p-Ge and n-InGaAs MOSFETs outperform their equally sized Si counterpart and superior performance of Ge/In GaAs-based CMOS is obtained.
Abstract: CMOS circuits built using Ge-channel p-MOSFETs and InGaAs-channel n-MOSFETs have shown promise for high-performance logic applications. In this paper, we investigate for the first time the performance of such circuits using extensive device simulations. The digital performance of a CMOS inverter is evaluated in terms of noise margins, rise time, fall time, and propagation delay. Furthermore, frequency of oscillations of a three-stage ring oscillator is obtained for varying ratio of the channel width of the p- and the n-MOSFETs, respectively (Wp/Wn). Our investigations reveal that the CMOS circuits comprising of p-Ge and n-InGaAs MOSFETs outperform their equally sized Si counterpart. Moreover, superior performance of Ge/InGaAs-based CMOS is obtained for In0.75Ga0.25 As channel with width ratio (Wp/Wn) of 10: 1. Also, Ge/InGaAs CMOS is found to lose its advantages over Si CMOS for $D_{it}$ exceeding 5 × 10 12 eV−1 · cm−2.

16 citations

Journal ArticleDOI
TL;DR: In this article, a multi-channel MOSFET (MC-MOS-FET) was proposed for RF amplifier applications, which has two vertical gates placed in trenches creating multiple channels in p-body for parallel conduction of drain current.

13 citations

Journal ArticleDOI
TL;DR: In this paper, a physics-based electron-mobility model including remote Coulomb scattering by fixed charge in high-k dielectric and remote interface roughness scattering originated from the fluctuation of high- k /interlayer interface is established for InGaAs MOSFET, and the validity of the model is confirmed by good agreement between simulated results and experimental data.
Abstract: A physics-based electron-mobility model including remote Coulomb scattering by fixed charge in high- k dielectric and remote interface-roughness scattering originated from the fluctuation of high- k /interlayer interface is established for InGaAs MOSFET, and the validity of the model is confirmed by good agreement between simulated results and experimental data. Effects of structural and physical parameters of the devices on the electron mobility are analyzed using the model, and the results show that smoother high- k /interlayer interface, reasonably high permittivities for the interlayer and high- k dielectric, and less fixed charge in the high- k dielectric are desired to enhance the electron mobility and simultaneously keep further scaling of equivalent oxide thickness.

12 citations

References
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Journal ArticleDOI
TL;DR: In this paper, the dual material gate (DMG) FET was proposed and demonstrated, where the gate consists of two laterally contacting materials with different work functions, such that the threshold voltage near the source is more positive than that near the drain, resulting in a more rapid acceleration of charge carriers in the channel.
Abstract: A generic new type of field effect transistor (FET), the dual material gate (DMG) FET, is proposed and demonstrated. The gate of the DMGFET consists of two laterally contacting materials with different work functions. This novel gate structure takes advantage of material work function difference in such a way that the threshold voltage near the source is more positive than that near the drain (for n-channel FET, the opposite for p-channel FET), resulting in a more rapid acceleration of charge carriers in the channel and a screening effect to suppress short-channel effects. Using the heterostructure FET as a vehicle, the principle, computer simulation results, design guidelines, processing, and characterization of the DMGFET are discussed in detail.

450 citations


"Impact of Different Barrier Layers ..." refers methods in this paper

  • ...A decrease in gd is expected by adopting SCE reduction techniques such as use of a dual-material gate in the device [17], [18]....

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Journal ArticleDOI
Y. Xuan1, Yanqing Wu1, H.C. Lin1, Tian Shen1, P. D. Ye1 
TL;DR: In this article, high performance inversion-type enhancement-mode n-channel In053Ga047As MOSFETs with atomic layer-deposited (ALD) Al2O3 as gate dielectric are demonstrated.
Abstract: High-performance inversion-type enhancement-mode n-channel In053Ga047As MOSFETs with atomic-layer-deposited (ALD) Al2O3 as gate dielectric are demonstrated The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general A 05-mum gate-length MOSFET with an Al2O3 gate oxide thickness of 8 nm shows a gate leakage current less than 10-4 A/cm2 at 3-V gate bias, a threshold voltage of 025 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V The midgap interface trap density of regrown Al2O3 on In053Ga047As is ~14 x 1012/cm2 ldr eV which is determined by low-and high-frequency capacitance-voltage method The peak effective mobility is ~1100 cm2 / V ldr s from dc measurement, ~2200 cm2/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 05-10-MV/cm effective electric field

180 citations


"Impact of Different Barrier Layers ..." refers background or methods in this paper

  • ...Most importantly, a large indium content in the channel material enhances the electron mobility in the channel [3], [4], [11]–[13], and also increases the conduction band offset between the channel and barrier layer, as shown in Table I, resulting in improved carrier confinement....

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  • ...Different mobility versus effective electric field and inversion charge density curves for different molar contents of indium in the InGaAs channel as reported in [3], [4], and [11]–[13] are used to extract such model parameters....

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Journal ArticleDOI
TL;DR: In this article, the energy-band gap of the Al2O3-InGaAs interface was determined to be 3.83±0.05eV by x-ray photoelectron spectroscopy.
Abstract: The valence-band offset has been determined to be 3.83±0.05eV at the atomic-layer-deposition Al2O3∕InGaAs interface by x-ray photoelectron spectroscopy. The Au–Al2O3∕InGaAs metal-oxide-semiconductor diode exhibits current-voltage characteristics dominated by Fowler-Nordheim tunneling. From the current-voltage data at forward and reverse biases, a conduction-band offset of 1.6±0.1eV at the Al2O3–InGaAs interface and an electron effective mass ∼0.28±0.04m0 of the Al2O3 layer have been extracted. Consequently, combining the valence-band offset, the conduction-band offset, and the energy-band gap of the InGaAs, the energy-band gap of the atomic-layer-deposited Al2O3 is 6.65±0.11eV.

179 citations

Journal ArticleDOI
TL;DR: In this article, the dielectric constants of GaAs, CdTe, and ZnSe and their temperature dependences were found from low-frequency capacitance measurements.
Abstract: The dielectric constants of GaAs, CdTe, and ZnSe and their temperature dependences were found from low‐frequency capacitance measurements. From 100 to 300 °K the dielectric constants vary linearly with temperature. No electric field dependence was found up to 104 V/cm, nor frequency dependence between 20 Hz and 1 MHz. The dielectric constants extrapolated linearly to 0 °K are 12.35±0.09, 10.31±0.08, and 8.80±0.07 for GaAs, CdTe, and ZnSe, respectively. The temperature coefficients λ (≡e (0)−1 de/dt) are 2.01×10−4/°K, 2.27×10−4/°K, and 1.71×10−4/°K, respectively, with an accuracy of ±0.02×10−4/°K.

154 citations


"Impact of Different Barrier Layers ..." refers methods in this paper

  • ...Since InGaAs is an alloy, its dielectric constant is computed using linear interpolation among the corresponding reported parameters of the constituents GaAs and InAs [6], [7]....

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Journal ArticleDOI
TL;DR: In this article, the resistivity, crystallinity, and work function of Tantalum nitride (TaN) films were investigated as a function of nitrogen flow rate, and the work function increased to 4.5-4.7 eV with less dependency on the nitrogen flow rates.
Abstract: Tantalum nitride (TaN) films were prepared by reactive sputtering in a gas Ar and N2 for gate electrode applications. Resistivity, crystallinity, and work function of the films were investigated as a function of nitrogen flow rate. As the nitrogen flow rate increased from 0 to 20 sccm, the resistivity of as-deposited TaN films increased from 132 to 1.4×105 μΩ cm. With a nitrogen flow rate of 8 and 10 sccm, the fcc TaN phase was obtained. The work function of the TaN films was investigated using TaN-gated nmetal–oxide–semiconductor capacitors with SiO2 gate dielectrics of various thicknesses. As the nitrogen flow rate increased from 4 to 12 sccm, the work function decreased from 4.1 to 3.4 eV for as-deposited films. After annealing at 950 °C for 1 min, the work function increased to 4.5–4.7 eV, with less dependency on the nitrogen flow rate.

96 citations