Impact of Dynamic Voltage Scaling and Thermal
Factors on FinFET-based SRAM Reliability
F. R. Rosa
1
, R. M. Brum
2
, G. Wirth
2
, L.Ost
3
, and R. Reis
1
1
PGMICRO\PPGC Instituto de Informtica, Universidade Federal do Rio Grande do Sul
{frdarosa,reis}@inf.ufrgs.br
2
Departamento de Engenharia Eletrica, Universidade Federal do Rio Grande do Sul
{brum,wirth}@inf.ufrgs.br
3
Department of Engineering, University of Leicester, Leicester, United Kingdom
luciano.ost@leicester.ac.uk
Abstract—FinFET technology appears as an alternative so-
lution to mitigate short-channel effects in traditional CMOS
down-scaled technology. Emerging embedded systems are likely
to employ FinFET and dynamic voltage scaling (DVS), aiming to
improve system performance and energy-efficiency. This paper
claims that the use of DVS increases the susceptibility of FinFET-
based SRAM cells to soft errors under radiation effects. To in-
vestigate that, a methodology that allows determining the critical
charge according to the dynamic behaviour of the temperature as
a function of the voltage scaling is used. Obtained results support
our claim by showing that both temperature and voltage scaling
can increase up to five times the susceptibility of FinFET-based
SRAM cells to the occurrence of soft errors.
I. INTRODUCTION
The scaling of traditional CMOS technology is facing
reliability and power issues due to the short channel and
the leakage effects [1], [2]. In this context, semiconductor
foundries, such as Intel, TSMC and Global Foundries, have
been adopting the multi-gate, nonplanar transistor technology
known as Fin Field-Effect Transistor, or FinFET [3], [4].
The FinFET is pointed as a promise alternative to improve
the performance and energy tradeoffs, while keeping the
compatibility with CMOS process [5].
Emerging embedded System-on-Chip (SoC) will employ
FinFET and dynamic voltage scaling (DVS), aiming to im-
prove system performance and energy-efficiency. DVS reduces
energy consumption by lowering the supply voltage and sys-
tem operating frequency. However, the use of DVS has a direct
influence on the sensitivity of both CMOS-based [6]–[8] and
FinFET-based SRAM cells to Single Event Upsets (SEUs).
Researches have been analyzed radiation effects as SEUs
in bulk CMOS, and more recently, in FinFET, showing the
susceptibility of both technologies to neutron or alpha particles
strikes [9]–[11]. Excluding the work proposed in [12], other
approaches consider only static variations of supply voltage
and temperatures.
This paper contributes by adapting the methodology pro-
posed in [12] to inspect the FinFET-based SRAM cells vulner-
ability considering critical charge under dynamic temperature
and DVS variations. Summarizing, this paper contributes in
the following aspects:
• inclusion of FinFET-based SRAM cell and temperature-
power model calibration,
• methodology validation using 20nm PTM (Predictive
Technology Model) FinFET technology, considering four
voltage scaling scenarios,
• automatization and optimization of proposed methodol-
ogy for CMOS and FinFET technologies.
Section II describes the proposed methodology. Obtained
results considering the 20nm technology for four different volt-
age scaling scenarios are presented in Section III. Afterwards,
conclusions and perspectives are discussed in Section IV.
II. PROPOSED METHODOLOGY TO EVALUATE CRITICAL
CHARGE (Qcrit) OF FINFET-BASED SRAM CELLS
We develop a methodology to follow the SEU sensibility
of a FinFET SRAM bit cell over a time interval. The SEU
sensibilty take into account factors as temperature and supply
voltage. In this context, we define SEU sensibility as the
minimum amount of collected charge in the transistor junction
needed to cause a bit-flip, designated critical charge (Qcrit).
Our proposed methodology consists on pre-characterizing
the FinFET SRAM bit cell Qcrit under a broad range of
supply voltage and temperature conditions, thus creating a
two-dimensional matrix. This profile matrix contains the Qcrit
information for every operating point (i.e. voltage and tem-
perature), respecting a minimum granularity. Afterward, we
correlate a temporal SRAM cell simulation in SPICE level
with its SEU sensibility by accessing this profile matrix for
every time step as the flow displayed by Fig. 1 (a).
The promoted methodology has five steps: The first step
consists in embed a source current in the FinFET SRAM
description to model the SEU fault injection by injecting a
transient current pulse in the cell node, as illustrated in Fig. 1
(b). We use a double exponential current model for the fault
injection, as defined in equation 1 and display in Fig. 1 (c).
To acquire the Qcrit value we search for the smallest
value of
R
I
p
(t)dt by slightly changing the curve parameters,
V
HI
Time
Time
V
LO
T
HI
T
LO
Worst
Time
Best
Resulting
Qcrit trace
Temp. →
Volt. →
Qcrit
Profile
Volt.
Temp.
Qcrit
Critical charge (CC)
Q
min
Q
max
Q = I
p
(t)dt
WL = disabled
I
p
(t)
BL
/BL
∫
(b)
(c)
(d)
G
T
|P
XTOR
|
R
T
C
T
V
T
V
T0
T
R
TC
...
+
+
(a)
G
B
T
D
S
(e)
G
D
S
B
Fig. 1. Proposed methodology for profiling the critical charge: (a) Deriving time-dependent critical-charge curves using a pre-characterizing profile matix;
(b) Bit-cell simulation with SEU emulated by current injection; (c) Relationship between critical charge and the injected current; (d) Binary search for the
critical charge; (e) Self-heating transistor model.
consequently the total injected charge as highlighted in red(
see Fig. 1 (c)). This approach enables find out the smallest
amount of collected charge that triggers an SRAM bit-flip for
a defined temperature and voltage supply.
I
p
(t) = I
0
(e
t
τ
f all
− e
t
τ
rise
)
(1)
Next step, we deploy the search methodology to find the
Qcrit for a broad range of temperature and voltage conditions,
generating a Qcrit profile matrix. The Qcrit search employs
a bisection search method. This method works by halving
the search interval at each iteration until it reaches a small
error from the desired value, pictured in Fig. 1 (d). This
step is then repeated for each supply voltage and temperature
condition, allowing us to construct a profile similar to the one
represented by Fig. 1 (a), where a darker shades represents the
smaller Qcrit and, consequently, a more sensible cell. While
the example shown in this picture is symmetrical with respect
to the main diagonal, temperature and voltage may affect the
Qcrit differently, as shown in the next section. The worst case
will be located in the upper-left corner, as higher temperatures
and lower voltages are expected to reduce the Qcrit. However,
seldom chips will work in such critical conditions, at least not
for a long time. To estimate the timeframe, during which the
circuit is exposed to this situation, we may combine the Qcrit
profile with time-dependent supply voltage and temperature
curves.
Afterward in the third step, we introduce a simple self-
heating model for the transistors, similar to the one proposed
by Bielefeld et al. [13] to mimic a temperature behavior
following the supply voltage wave, its schematic is shown in
Fig. 1 (e). The passive elements in this model are related to
the transistor’s physical layers, the resistive elements related
to the thermal conductivity, whereas capacitors are related
to the specific heat and mass of these materials, and active
elements will be related to the power-temperature relationship
of the transistor. To obtain an accurate numerical result, a
proper calibration of these elements would be required. For
the purpose of proving that DVS impacts on the circuit’s
reliability, we are only interested in the ratio between the time
constants associated with the thermal circuit (RCtemperature)
and the voltage supply circuit. By using this model, the
associated effect on the bit cell temperature can be obtained
and crossed with the Qcrit profile. To account for the power
supply capacitance, we introduce a lumped capacitor in the
power line.
Fourth step: We simulate the SRAM cell (attached with the
power model) for a supply voltage wave to generate a temporal
voltage and temperature trace. This supply voltage has two
distinct phase: In the first phase, a high throughput memory
access in overdrive Vdd, driving more current, and, therefore,
increasing the SRAM cell temperature. Our methodology uses
a 0.5 activity factor, a good average approximation (i.e. neither
conservative nor pessimistic) for the least significant bits in
a cache memory [14]. In the second phase, the memory
voltage supply is reduced to a low power level, which is
defined according to the adopted technology (e.g. 0.5V for
20nm). The high temperature (T
HI
in Fig. 1 (a)) during the
high memory usage (V
HI
in Fig. 1 (a)) is conducted through
the chip package. At this point, the SRAM Cell has a low
voltage supply and a high temperature, therefore, rising by
several times its vulnerability to SEU. The period where the
Qcrit is smaller than expect bounds the worst case, which
is defined according to the confluence of temperature and
low Vdd. The energy dissipation occurs according to the
RC
temperature
and its ratio with the RC
electric
, which is
determined by the technology construction. The last step, these
two traces are analyzed at each timestep, consulting the profile
matrix to acquire the Qcrit at this particular temperature and
voltage point. Thus creating a trace for the SEU sensibility
of a FinFET SRAM bit cell as shown in Fig. 1 (a). In the
next section, we present some of the obtained results for the
20nm Predictive Technology Model (PTM) from Arizona State
University [15].
III. EXPERIMENTAL SETUP AND RESULTS
In order to exploit the proposed methodology, we will
present results for four different DVS scenarios. Our experi-
mental setup uses the Cadence SPECTRE simulator to perform
all experiments in an Intel Xeon L5520 2.27 GHz with 32 GB
RAM. The 6T-SRAM FinFET cell use two inverters, and two
passing gates as the case study. The PTM defines the height
of the Fin (28nm), the thickness of the Fin (15nm), and gate
length (24nm). Our cell uses a 48nm width with minimum
length. Fig. 2 shows the Qcrit matrix profile obtained for
the 20nm PTM technology, with a resolution of 0.001 V and
0.1 C, covering temperatures ranging from -40C to 125C and
supply voltages ranging from 0.45 V to 1.25 V.
Fig. 2. Critical charge profile obtained for the FinFET 6T-SRAM cell built
for the PTM 20nm technology.
From this profile matrix, it becomes apparent that the
supply voltage has a stronger influence than the temperature
over the considered operational ranges. Notwithstanding, while
operating at higher voltages, the circuit sensibility is firmly in-
fluenced by the temperature: moving from room temperature to
125C can almost halve the Qcrit of the bit cell. Indeed, higher
supply voltage enhances radiation resilience as improves the
noise margin, reaching five times between extreme points.
Nevertheless, dynamic and static power dissipation effects are
directly related to the supply voltage and therefore designers
often deploy DVS to reduce its power consumption. When
applying DVS, both effects of temperature and supply voltage
are seen in a dynamic way where there are periods when the
voltage is constant, and the temperature behaves dynamically
and periods that the supply voltage and temperature are
changing to adjust to the DVS.
The Fig. 3 displays (from top to down) the voltage wave,
the resulting temperature from this context according to our
model, Qcrit value, and Qcrit zoom for ratios from 1 to
100K. The first scenario (a) maintains a constant overdrive
voltage of 1.2V until 10µs, consequently heating the cell, then
lowering to 0.5V until the simulation ends. Where it releases
the accumulated thermal energy through the chip package. As
this
RC
temperature
RC
electric
ratio increases the heat dissipates faster. A
rapid heat dissipation reduces the coincidence between the low
voltage supply and high temperature. In this scenario, shortly
after the supply voltage transition has its SEU sensibility
increased four times, additionally, the confluence of low supply
voltage and higher temperature creates an even greater SEU
sensitivity.
The second scenario (b) (see Fig. 3) adds a second over-
drive period from 20µs to 30µs, consequently the SRAM
experiences a reheating interval. At this moment, with lower
temperatures and higher supply voltage, the SRAM cell has
an overprotection (i.e. seven times) against particles strikes
compared with the previous moments. This supply voltage
rapidly leads to a cell warming, decreasing again the Qcrit. A
shorter low Vdd interval will increase the minimal temperature
reach while in low supply voltage. Additionally, the overdrive
interval leads to a significant reheating. A longer high Vdd
period reduces the cell vulnerability, besides the temperature
increase as the result of the higher importance of supply
voltage over temperature to the SEU sensitivity.
The third scenario (C) proposes a two-step voltage scaling,
first passing to the nominal voltage (i.e. 0.9V) in 20µs and
then an overdrive voltage from 30µs until 40µs. The supply
voltage effect in the SEU sensitivity is not linear, as in the
first transition from 0.5V to 0.9V the Qcrit increases from
0.43 fC to 1.5 fC while transitioning to 1.2V its value grows
three times. In the fourth scenario (d) a constant square wave
with 20µs period excites the SRAM cell, nevertheless in this
scenario the maximum supply voltage is the nominal Vdd.
Higher
RC
temperature
RC
electric
ratio increases the temperature swing,
increasing SEU sensitivity unpredictability.
IV. CONCLUSION
In this work, we use a methodology to determine the Qcrit
of FinFET SRAM bit cells under voltage scaling, considering
10 20 30 40
0.5
1
Voltage (V)
10 20 30 40
0
50
100
Temp. (+C)
10 20 30 40
0
5
Qcrit (fC)
10 20 30 40
42.5
43
Qcrit (fC/100)
10 20 30 40
0.5
1
Voltage (V)
10 20 30 40
0
50
100
Temp. (+C)
10 20 30 40
0
5
Qcrit (fC)
10 20 30 40
42.5
43
Qcrit (fC/100)
(a) (b)
(c)
(d)
20 40 60
0.5
1
Voltage (V)
20 40 60
50
100
Temp. (+C)
20 40 60
0
5
Qcrit (fC)
20 40 60
42.5
43
Qcrit (fC/100)
20 40 60 80
0.5
1
Voltage (V)
20 40 60 80
40
60
Temp. (+C)
20 40 60 80
0
1
2
Qcrit (fC)
20 40 60 80
42.8
43
Qcrit (fC/100)
Fig. 3. (from top to down) voltage waveform, temperature, critical charge, and a critical charge zoom for proposed DVS scenarios using our method.
transient temperature effects. By introducing a temperature-
power model, we demonstrated that FinFET-based SRAM cells
are more sensitive to radiation when the supply voltage is
transitioning from a higher to a lower voltage, reducing the
Qcrit few times. SEU sensitivity is highly dependable on
parameters as temperature, supply voltage and their temporal
confluence, as see in Fig. 3. Embedded systems dynamically
adjust the supply voltage according to these parameters, nor-
mally controlled by off-chip management units, which have
little or no configuration options available to the user.
Although DVS impacts directly the SEU sensitivity, its
deployment is imperative in nowadays embedded systems,
which are mostly battery-driven devices. The use of DVS
may expose particular code fragments to the occurrence of
soft errors. In this context, the system engineer requires a
greater understanding of the DVS impact on the soft error
sensitivity for a given system. Solutions for this challenge may
include either delaying supply voltage transition for radiation-
hardened circuits, or using a gradual step-based supply voltage
transition. In the future, we intend to study new approaches
to radiation-aware voltage scaling.
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