Impact of gate underlap on gate capacitance and gate tunneling current in 16 nm DGMOS devices
04 Oct 2004-pp 94-95
TL;DR: In this article, the impact of gate underlap on the effective gate capacitance and gate tunneling current in DGMOS devices has been demonstrated and it is shown that in scaled devices, fringing capacitance dominates the effective gating capacitance.
Abstract: In this paper, the impact of gate underlap on the effective gate capacitance and gate tunneling current in DGMOS devices has been demonstrated. It is shown that in scaled devices, fringing capacitance dominates the effective gate capacitance. Hence with optimum underlap the effective gate capacitance can be reduced thereby reducing the delay and power. Gate underlapping also reduces gate direct tunneling current in the off-state.
Citations
More filters
TL;DR: In this paper, the impact of gate electrode thickness and gate underlap on the fringe capacitance of double-gate MOS transistors was analyzed and an analytical model was proposed to estimate the marginal capacitance.
Abstract: We analyze the impact of gate electrode thickness and gate underlap on the fringe capacitance of nanoscale double-gate MOS (DGMOS) transistors. We propose an analytical fringe capacitance model considering gate underlap and finite source/drain length. A comparison with the simulation results show that the model can accurately estimate the fringe capacitance of the device. We show that an optimum gate underlap can significantly reduce the fringe capacitance resulting in higher performance and lower power consumption. Also, the effects of process variation in gate underlap devices are discussed. Simulation results on a three-stage ring oscillator show that with optimum gate underlap 32% improvement in delay can be achieved.
194 citations
Cites background from "Impact of gate underlap on gate cap..."
...It is also shown that the fringe capacitance reduces with the increase in gate underlap [5]....
[...]
TL;DR: In this article, the authors proposed to optimize the gate sidewall offset spacer thickness to simultaneously minimize leakage current and drain capacitance to on-current ratio in FinFETs.
Abstract: In this paper, we propose a methodology to model and optimize FinFET devices for robust and low-power SRAMs. We propose to optimize the gate sidewall offset spacer thickness to simultaneously minimize leakage current and drain capacitance to on-current ratio in FinFET. With the source/drain extension doping controlled at the outer edges of the spacer, the thickness of the spacer determines the channel length. Optimization reduces the sensitivity of the device threshold voltage to the fluctuations in silicon thickness (by 32%) and gate length (by 73%). Our analysis shows that optimization of spacer thickness results in 65% reduction in SRAM cell leakage and improves cell read-failure probability (by 200 X) compared to conventional FinFET SRAM. Access time of an SRAM cell designed with optimized devices is comparable to conventional SRAM. We also compared the optimized-spacer-thickness SRAM cell with one designed using longer gate length and minimum-spacer-thickness transistors. The long-channel-device-based SRAM cell is marginally robust than optimized SRAM; however, increased gate-edge direct-tunneling leakage and parasitic capacitances degrade the power consumption and access time.
95 citations
Cites background from "Impact of gate underlap on gate cap..."
...Increase in ∆Lsp also reduces Iedt because of the reduced gate-S/D overlap length (Lov) [12]....
[...]
TL;DR: In this article, an analytical model was proposed to compute the potential distribution in gate underlap double-gate symmetric MOS transistors in the sub-reshold condition Ggs < Vth.
Abstract: We propose an analytical model to compute the potential distribution in gate underlap double-gate symmetric MOS transistors in the subthreshold condition Ggs < Vth . Gate underlap increases the effective channel length, which results in reducing the short-channel effect and, hence, relaxing the constraint on silicon body thickness. We use the proposed model to obtain suitable gate underlap length and silicon thickness for iso subthreshold slope and drain-induced-barrier lowering. Gate fringing field, modulating the potential in gate underlapped regions, is modeled using a conformal mapping technique. Extensive simulations were carried out to confirm the validity of our model to gate lengths ~20 nm.
64 citations
Cites background from "Impact of gate underlap on gate cap..."
...2) also reduces gate edge direct tunneling leakage [9] and gate sidewall fringe capacitance, resulting in an improved circuit performance [10], [11]....
[...]
TL;DR: In this paper, the sub-threshold analog/RF performance for underlap double-gate (UDG) NMOSFETs using high dielectric constant (k) spacers was investigated.
Abstract: This paper presents a systematic study of the subthreshold analog/RF performance for underlap double gate (UDG) NMOSFETs using high dielectric constant (k) spacers. The conventional UDG-NMOSFETs offer reduced short-channel effects along with improved subthreshold analog/RF performance at a cost of higher distributed channel resistance and low on current. In this paper, we show that these drawbacks can be alleviated effectively by using high-k spacers without any severe degradation in the subthreshold analog/RF performance. In order to show the improvement in the device performance, we have studied the effect of high-k spacers on different subthreshold analog figures of merit such as the transconductance, transconductance generation factor, output resistance, and the intrinsic gain for different values of k . Moreover, we have analyzed the RF performance as a function of intrinsic capacitance and resistance, transport delay, inductance, cutoff frequency, and the maximum oscillation frequency. In order to assess the gain bandwidth (GBW) product, the circuit implementation of the UDG-NMOSFETs with different high-k spacers was performed on a common source amplifier. Our results show an improvement in the GBW of about 38% for the devices with high- k spacers compared to its low- k counterpart.
56 citations
TL;DR: It is demonstrated how device subthreshold leakage current and subth threshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry and gate work function engineering in combination with gate underlap engineering.
27 citations
References
More filters
TL;DR: In this article, a spacer patterning technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-7 nm structures with conventional dry etching.
Abstract: A spacer patterning technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-7 nm structures with conventional dry etching. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields critical dimension (CD) variations of minimum-sized features much smaller than that achieved by optical or e-beam lithography. In addition, it also provides a doubling of device density for a given lithography pitch. This method is used to pattern silicon fins for double-gate metal-oxide semiconductor field effect transistors (MOSFETs) (FinFETs) and gate electrode structures for ultrathin body MOSFETs. Process details are presented.
281 citations
TL;DR: In this paper, a quantum capacitance-voltage (C-V) modeling in depletion and inversion, incorporating the gate depletion effect, is presented, which enables fast and accurate extraction of the electrical thickness of gate oxide in deep submicron MOSFETs.
Abstract: Presented in this paper is a quantum capacitance-voltage (C-V) modeling in depletion and inversion, incorporating the gate-depletion effect. The model enables fast and accurate extraction of the electrical thickness of gate oxide in deep submicron MOSFETs. The main quantum effect consists of the inversion capacitance of two-dimensional (2-D) electrons masking the true gate-oxide thickness, t/sub OX/. The quantum mechanical and gate depletion effects necessitate 6-10 /spl Aring/ equivalent oxide thickness correction, which is important for a t/sub OX/ of 4 nm or less. The classical C-V analysis is compared with the quantum results in the light of the data, highlighting the difference between the models. The model is shown in good agreement with experiments and also with numerically calculated results.
19 citations