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Proceedings ArticleDOI

Impact of NBTI induced variations on FinFET based Vernier delay line time to digital converter

01 Mar 2017-pp 122-125

Abstract: The Negative Bias Temperature Instability (NBTI) is one of the serious reliability issues of the p-type MOS based transistors. The downscaling of gate oxide thickness to reestablish the gate voltage controllability over the channel adversely affects the reliability of the devices and circuits. The multigate transistors such as FinFET which shows superior device scalability over the planar MOSFET are also severely affected by the NBTI effects in the nanoscale regime. The time to digital converter (TDC) is a signal conditioning circuit which is used to convert the specified time interval between two events into the digital codes. The proper functioning of the TDC is based on accuracy of the propagation delay of its designed delay lines. The degradation of the delay in the delay lines due to NBTI lead to improper code conversions. The Vernier delay line TDC is designed using the 30 nm Triple Gate FinFET technology with high resolution of 10 ps. The effect of NBTI degradation over the FinFET based Vernier delay line TDC in the critical nodes is analyzed. The occurrence of offset error, increase in the non linearity and degradation of resolution are observed due to the NBTI degradation.
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Journal ArticleDOI
Timo Rahkonen1, Juha Kostamovaara1Institutions (1)
Abstract: The basic advantages and limitations of using integrated digital CMOS delay lines for the digitization of short time intervals are discussed. Accuracies of 6-7 b and single-shot resolutions from 0.1 to 10 ns are demonstrated to be realizable using fully integrated, tapped, and voltage-controlled CMOS delay lines as a time base for the measurement. >

227 citations


"Impact of NBTI induced variations o..." refers methods in this paper

  • ...The resolution of the TDC can be improved using the vernier method [7]....

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Proceedings ArticleDOI
Yao Wang1, Sorin Cotofana1, Liang Fang2Institutions (2)
08 Jun 2011
TL;DR: The model is based on the reaction-diffusion theory and extends it such that it covers the FinFET specific geometrical structures and it is computationally efficient, which makes it suitable for utilization in reliability-aware architectures as reliability prediction/assesment kernel for lifetime reliability management mechanisms.
Abstract: As planar MOSFETs is approaching its physical scaling limitation, FinFET becomes one of the most promising alternative structure to keep on the industry scaling-down trend for future technology generations of 22 nm and beyond. In this paper, we propose a unified reliability model of Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) for double-gate and triple-gate FinFETs, towards a practical reliability assessment method for future FinFETs based circuits. The model is based on the reaction-diffusion theory and extends it such that it covers the FinFET specific geometrical structures. Apart of introducing the reliability model we also investigate the circuit performance degradation due to NBTI and HCI in order to create the premises for its utilization for assessing and monitoring the Integrated Circuits (ICs) aging process. To validate our model we simulated NBTI and HCI degradation and compared the obtained V th shift prediction with the one evaluated based on experimental data. The simulations suggest that our model characterize the NBTI and HCI process with accuracy and it is computationally efficient, which makes it suitable for utilization in reliability-aware architectures as reliability prediction/assesment kernel for lifetime reliability management mechanisms.

63 citations


"Impact of NBTI induced variations o..." refers background in this paper

  • ...In this work, the experimental data [9-10] for the variation of threshold voltage...

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Journal ArticleDOI
Abstract: Negative-bias temperature-instability (NBTI) characteristics are carefully studied on SOI and body-tied pMOS FinFETs for the first time. It was observed that a narrow fin width degraded device lifetime more than a wider fin width. Electrons generated by the NBT stress are accumulated at the center of a silicon fin and cause energy-band bending. This results in an incremental hole population at the interface. The energy band is bent more steeply at the narrow fin than at the wide fin by the accumulated electrons. A body-tied FinFET shows better immunity to NBT stress due to a substrate contact.

40 citations


Journal ArticleDOI
Vita Pi-Ho Hu1, Ming-Long Fan1, Chien-Yu Hsieh1, Pin Su1  +1 moreInstitutions (1)
Abstract: This paper analyzes the impacts of intrinsic process variations and negative bias temperature instability (NBTI)/positive BTI (PBTI)-induced time-dependent variations on the stability/variability of 6T FinFET static random access memory (SRAM) cells with various surface orientations and gate dielectrics. Due to quantum confinement, (110)-oriented pull down n-channel FETs with fin line-edge roughness (LER) show larger Vread,0 and Vtrip variations, thus degrading READ static noise margin (RSNM) and its variability. Pull-up p-channel FETs with fin LER that are (100)-oriented show larger Vwrite,0 and Vtrip variations, hence degrade the variability of WRITE SNM. The combined effects of intrinsic process variations and NBTI/PBTI-induced statistical variations have been examined to optimize the FinFET SRAM cells. Worst-case stress scenario for SNM stability/variability is analyzed. With the presence of both NBTI and PBTI in high-fe metal-gate FinFET SRAM, the RSNM suffers significant degradation as Vread,0 increases, whereas Vtrip simultaneously decreases. Variability comparisons for FinFET SRAM cells with different gate stacks (SiO2 and SiO2/HfO2) are also examined. Our paper indicates that the consideration of NBTI/PBTI-induced temporal variation changes the optimal choice of FinFET SRAM cell surface orientations in terms of the μ/σ ratio in RSNM.

36 citations


"Impact of NBTI induced variations o..." refers methods in this paper

  • ...The NBTI degradation in the FinFET based various VLSI circuits has been analysed in the literatures [4-6] and shown to cause performance degradation and failure of the circuits....

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Journal ArticleDOI
Abstract: Three-dimensional vertical double-gate (FinFET) devices with a high aspect ratio (Si-fin height/width = Hfin/Wfin = 86 nm/17 nm) and a gate nitrided oxide of 14 Aring thickness have been successfully fabricated. Reliability characterizations, including hot-carrier injection (HCI) for NMOS FinFETs and negative bias temperature instability (NBTI) for PMOS FinFETs, are carried out in order to determine their respective lifetimes. The predicted HCI dc lifetime for a 50-nm gate-length NMOS FinFET device at the normal operating voltage (Vcc) of 1.1 V is 133 years. A wider fin-width (27 nm) PMOS FinFET exhibits promising NBTI lifetime such as 26.84 years operating at Vcc = 1.1 V, whereas lifetime is degraded for a narrower fin-width (17 nm) device that yields 2.76 years of lifetime at the same operating voltage and stress conditions.

31 citations


"Impact of NBTI induced variations o..." refers background in this paper

  • ...Available: http://www.device.eecs.berkeley.edu/bsim/?page=BSIMCMG [9] Yao Wang, S. Cotofana and Liang Fang, "A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits," 2011 IEEE/ACM International Symposium on Nanoscale Architectures, San Diego, CA, 2011, pp. 175- 180....

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  • ...However, nanoscale FinFETs suffer from various reliability issues similar to planar MOSFET [1-3]....

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  • ...Keywords— NBTI; reliability; FinFET; time to digital converter I. INTRODUCTION The various short channel effects (SCE) in the planar MOSFETs are well suppressed in the multi-gate transistors such as FinFET....

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  • ...[6] Khalid, Usman, Antonio Mastrandrea and Mauro Olivieri, "Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops," Microelectronics Reliability, vol. 55, no. 12, pp. 2614-2626, Dec 2015....

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