Implementation of a 30 ps resolution time to digital converter in FPGA
16 Mar 2015-pp 12-17
TL;DR: With the high resolution TDC implemented, the design of a wide range and high resolution time to digital converter (TDC) on FPGA is presented and the same is demonstrated by performing the jitter measurements for the applied input pulse.
Abstract: We present the design of a wide range and high resolution time to digital converter (TDC) on FPGA. The multiplexers present in the dedicated carry chain on the FPGA are used in the presented architecture to create the delay line for the conversion. The TDC has been implemented on Spartan-3E FPGA from Xilinx and a resolution of about 30 ps was achieved. The TDC was calibrated against test signals generated using the digital clock manager and varying lengths of wire to generate the controlled delays. With the high resolution TDC implemented, we have realized a wide range (coarse grain and fine grain) TDC and demonstrated the same by performing the jitter measurements for the applied input pulse.
Citations
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TL;DR: In this paper, the authors discuss the most recent developments in CMOS TDCs, with an emphasis on ring-oscillator-based TDC and its variants, due to their suitability for array designs with less area overhead.
Abstract: Time-to-digital converters (TDCs) are increasingly used as building blocks in biomedical imaging, digital communication, and measurement instrumentation systems. When fabricated in deep-submicrometer (DSM) CMOS technology, TDCs have outstanding time stamping capability on the order of picoseconds. Typically, the timing resolution of a TDC directly determines the minimum resolvable spatial resolution in time-of-flight (ToF) measurements. It also limits the signal-to-noise ratio in ToF positron emission tomography and the in-band noise in an all-digital phase-locked-loop. In TDCs, good linearity and precision result in high measurement accuracy, while the detectable range is limited by its dynamic range. In addition, size and power consumption are of significant importance in large-scale array implementations such as image sensors. Here, we discuss the most recent developments in CMOS TDCs, with an emphasis on ring-oscillator-based TDC and its variants, due to their suitability for array designs with less area overhead. In addition, key performance metrics, and accurate cost-effective characterization methods will be discussed. Finally, future perspectives of CMOS TDCs will be highlighted.
65 citations
Cites methods from "Implementation of a 30 ps resolutio..."
...process to stabilize the delay of the delay lines in the FPGA devices [126]–[128], [130], [134], [136]....
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...The tapped delay line (TDL) architecture [123], [127], [131], [135], the VDL technique [122], [136], [137], the pulse-shrinking method [129], [134], the wave union method [124], [125], [132], [138], and the multiple interpolation approach [130], [131], [133], [135], [137], [139] were successfully implemented and demonstrated...
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TL;DR: This article presents and discusses the improvements on the FPGA-based TDC research, aiming to be a starting point for new studies on this field, with some guidelines for future research.
Abstract: Over the past few years, the gap between field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) performance levels has been narrowed due to the constant development of FPGA technology. The high performance, together with the lower development costs and a shorter time to market, turns FPGA-based platforms attractive for a huge range of applications, among them time-to-digital converters (TDCs). It is, therefore, important to analyze the evolution of FPGA-based TDCs to better understand where the research efforts should be focused in the near future. This article presents and discusses the improvements on the FPGA-based TDC research, aiming to be a starting point for new studies on this field, with some guidelines for future research. A state-of-the-art literature review on the FPGA-based TDC is presented, aiming to categorize and discuss the existing architectures. This discussion addresses architectures’ characteristics, limitations, and areas of application.
60 citations
Cites background from "Implementation of a 30 ps resolutio..."
...Architectures capable of reducing the length of the delay chains without compromising system resolution will become more popular and will be the focus of future research works [1], [103]....
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...3) Hybrid TDL: A recent trend is to pair a TDL with phased clocks’ architectures to reduce the TDL length, reducing hardware utilization and the effect of nonlinearities [22], [71], [77], [103], [113], [115]....
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10 Jun 2018
TL;DR: This paper examines the viability of using the DSP48A1 blocks present on Xilinx FPGAs to generate small delays, and ultimately concludes they are unsuitable in isolation due to the high differential non-linearity, but may be suitable as a semi-fine stage of a multi-stage TDC or when combined in an equivalent coding line.
Abstract: Time to digital conversion is an important task in many systems. It involves the conversion of time-based signals (as opposed to the amplitude-based signals in analog-to-digital conversion) into digital numbers so that a purely digital system may process them. This is widely used in rangefinders, all-digital phase-locked loops and quantum experiments. In order to obtain high-resolution time-to-digital conversion, the generation of small delays is necessary. This paper examines the viability of using the DSP48A1 blocks present on Xilinx FPGAs to generate these small delays, and ultimately concludes they are unsuitable in isolation due to the high differential non-linearity, but may be suitable as a semi-fine stage of a multi-stage TDC or when combined in an equivalent coding line.
13 citations
01 May 2017
TL;DR: Temporal characteristics extracted from the TDC implemented in a Xilinx ZYNQ family FPGA are reported and it is shown that the gain in the number of Flip-Flops and Lookup tables can reach factors of 85 and 2.1 respectively.
Abstract: In this paper, an area efficient time to digital converter (TDC) performing measurements between multiple hit signals is proposed. Our TDC is based on a delay line configured as a ring oscillator and a round tracker to count the number of iterations through the oscillator. Lookup tables configured as distributed RAMs and shift registers are used to sample the oscillator and the round tracker states whenever a transition on a signal occurs. A theoretical study is elaborated to estimate FPGA resources required to implement the proposed TDC in comparison with a multichannel basic RO-TDC. It is shown that the gain in the number of Flip-Flops and Lookup tables can reach factors of 85 and 2.1 respectively in an architecture made of a six-stage oscillator, a 32-state round tracker and 20 input hit signals. Temporal characteristics extracted from our TDC implemented in a Xilinx ZYNQ family FPGA are reported.
8 citations
Cites methods from "Implementation of a 30 ps resolutio..."
...In order to improve their resolution, some TDC circuits use the VDL (Vernier Delay Line) architecture [6], where both start and stop signals propagate in two chains composed of slightly different delay units....
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09 Jul 2018
TL;DR: A custom time-to-digital converter (TDC) designed to time tag individual photons from multiple single photon detectors with high count rate, continuous data logging and low systematics is described.
Abstract: We describe a custom time-to-digital converter (TDC) designed to time tag individual photons from multiple single photon detectors with high count rate, continuous data logging and low systematics. The instrument utilizes a taped-delay line approach on an FPGA chip which allows for sub-clock resolution of <100 ps. We implemented our TDC on a Re-configurable Open Architecture Computing Hardware Revision 2 (ROACH2) board which allows continuous data streaming and time tagging of up to 20 million events per second. The functioning prototype is currently set up to work with up to ten independent channels. We report on the laboratory characterization of the system, including RF pick up and mitigation as well as measurement of in-lab photon correlations from an incoherent light source (artificial star). Additional improvements to the TDC will also be discussed, such as improving the data transfer rate by a factor of 10 via an SDP+ Mezzanine card and PCIE 2SFP+ 10 Gb card, as well as scaling to 64 independent channels.
3 citations
References
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TL;DR: A high-resolution time-to-digital converter implemented in a general purpose field-programmable-gate-array (FPGA) is presented and dedicated carry lines of an FPGA are used as delay cells to perform time interpolation within the system clock period and to realize the fine time measurement.
Abstract: A high-resolution time-to-digital converter (TDC) implemented in a general purpose field-programmable-gate-array (FPGA) is presented. Dedicated carry lines of an FPGA are used as delay cells to perform time interpolation within the system clock period and to realize the fine time measurement. Two Gray-code counters, working on in-phase and out-of-phase system clocks respectively, are designed to get the stable value of the coarse time measurement. The fine time code and the coarse time counter value, along with the channel identifier, are then written into a first-in first-out (FIFO) buffer. Tests have been done to verify the performance of the TDC. The resolution after calibration can reach 50 ps
233 citations
"Implementation of a 30 ps resolutio..." refers background in this paper
...Similarly the fine grain TDC takes in the clock as the start input and input pulse as stop, and is designed to have the measurement range of 2.5 ns....
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TL;DR: A new design of a time-to-digital converter (TDC) implemented on an FPGA chip with amorphous antifuse structures is presented and the output from the delay line is obtained directly in "1-out-of-N" code and then converted to 6-bit natural binary.
Abstract: A new design of a time-to-digital converter (TDC) implemented on an FPGA chip with amorphous antifuse structures is presented. Time coding with 200-ps resolution (LSB), 10-ns range, and very short conversion time is realized by two tapped delay lines working in-a differential mode. Thanks to the local feedback loops, the output from the delay line is obtained directly in "1-out-of-N" code and then converted to 6-bit natural binary. Within the temperature range from 0/spl deg/C to 45/spl deg/C, the time offset at the output is constant, the resolution changes by /spl plusmn/0.02 LSB, and the offset-corrected integral linearity error is less than 1 LSB.
165 citations
"Implementation of a 30 ps resolutio..." refers background in this paper
...Once the count is sent, the coarse grain TDC will reset and start to begin a fresh counting....
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TL;DR: In this paper, the Wave Union TDC, a novel scheme of FPGA TDC to improve time measurement precision using multiple measurements, along with several other topics in FPGAs delay line based TDCs.
Abstract: This paper discusses implementation of the Wave Union TDC, a novel scheme of FPGA TDC to improve time measurement precision using multiple measurements, along with several other topics in FPGA delay line based TDCs. FPGA specific issues such as considerations on the delay line choice in different FPGA families and encoding logic are first examined. Next, common problems for both FPGA TDCs and ASIC TDCs such as schemes of coarse time counter implementation, bin-by-bin calibration and noise issues due to single ended signals are discussed. Several resource/power saving design approaches for various processing stages are described in the document.
157 citations
01 Oct 2007
TL;DR: This paper presents two high-resolution time-interval measuring system implemented in a SRAM-based FPGA device and shows their performance in terms of stability and resolution.
Abstract: In the past years, precise measurements of time intervals have been realized using methods such as time- stretching, Vernier and delay line. In this paper, we present two high-resolution time-interval measuring system implemented in a SRAM-based FPGA device. The two methods ought to be used for time interpolation within the system clock cycle. In the first method, dedicated carry lines are used to perform fine time measurement, while in the second one a differential tapped delay line is used. In this paper we compare the two architectures and show their performance in terms of stability and resolution.
41 citations