Implementation of a parallel signal processing system for all-purpose radar
26 Aug 2002-Vol. 2, pp 1465-1468
TL;DR: A DSP-based all-purpose radar parallel signal processing system (RPSPS) with high-speed real-time signal processing that makes it possible to implement the different signal processing tasks of other radar systems without changing the system hardware.
Abstract: A DSP-based all-purpose radar parallel signal processing system (RPSPS) with high-speed real-time signal processing is implemented to fulfil the all-purpose radar system reconfiguration. High performance DSP chips are used as the kernel processing nodes. By means of local shared memory, a global distributed memory parallel system and the pipelined dataflow method, it can perform absolutely parallel data processing of multi DSP. The finished system is simple in architecture, flexible in scale. The reconfiguration of this system through the embedded computer makes it possible to implement the different signal processing tasks of other radar systems without changing the system hardware.
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TL;DR: In this article, a modular, scalable and efficient hardware/software implementation of k-Nearest Neighbors (kNN) classifier targeting System on Chip (SoC) devices is presented.
Abstract: This paper presents kNN STreaming Unit For Fpgas (kNN-STUFF), a modular, scalable and efficient Hardware/Software implementation of k-Nearest Neighbors (kNN) classifier targeting System on Chip (SoC) devices. It takes advantage of custom accelerators, implemented on the reconfigurable fabric of the SoC device, to perform most of the classifier's workload, whereas the processor coordinates the accelerators and runs the remaining workload of the kNN algorithm. kNN-STUFF offers a highly flexible framework, where the designer has the possibility to define the number of parallel instances of the classifier and the parallelism within each instance. This capability allows creating the most suitable implementation for a target device of any size. Results show that kNN-STUFF, with 24 accelerators, attains performance improvements up to 67.4×, when compared to an optimized (-O3) software-only implementation of the kNN running on a single core of the ARM Cortex-A9 CPU. Furthermore, its energy efficiency improvements are as high as 50.6×.
25 citations
27 Mar 2010
TL;DR: It is proved by comparative experiments that performance indexes of the new ISABT are considerably improved and it basically meets the real-time requirement for robot visual processing.
Abstract: This paper deals with the improvement of free energy computing in segmentation algorithm according to the analysis of Image Segmentation Algorithm Based on Boltzmann Theory (ISABT) and a new one is proposed. It is proved by comparative experiments that performance indexes of the new algorithm are considerably improved. The parallel processing method of the algorithm which is applied to multi-processors is presented for solving the real-time problem, and then its feasibility is verified by experiments. The experiment shows that the improved ISABT with rapid parallel image processing greatly enhances the speed of segmentation with its segmentation effect assured. Compared with the original algorithm, the new one may reach a speed of 20ms/F for 480×320 image on the processing platform including eight pieces of TMS320DM642, and it basically meets the real-time requirement for robot visual processing.
1 citations
References
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TL;DR: A general overview of VLSI array processors and a unified treatment from algorithm, architecture, and application perspectives is provided in this article, where a broad range of application domains including digital filtering, spectrum estimation, adaptive array processing, image/vision processing, and seismic and tomographic signal processing.
Abstract: High speed signal processing depends critically on parallel processor technology. In most applications, general-purpose parallel computers cannot offer satisfactory real-time processing speed due to severe system overhead. Therefore, for real-time digital signal processing (DSP) systems, special-purpose array processors have become the only appealing alternative. In designing or using such array Processors, most signal processing algorithms share the critical attributes of regularity, recursiveness, and local communication. These properties are effectively exploited in innovative systolic and wavefront array processors. These arrays maximize the strength of very large scale integration (VLSI) in terms of intensive and pipelined computing, and yet circumvent its main limitation on communication. The application domain of such array processors covers a very broad range, including digital filtering, spectrum estimation, adaptive array processing, image/vision processing, and seismic and tomographic signal processing, This article provides a general overview of VLSI array processors and a unified treatment from algorithm, architecture, and application perspectives.
1,633 citations
01 Jan 1988
TL;DR: A general overview of VLSI array processors is provided and a unified treatment from algorithm, architecture, and application perspectives is provided.
Abstract: High speed signal processing depends critically on parallel processor technology. In most applications, general-purpose parallel computers cannot offer satisfactory real-time processing speed due to severe system overhead. Therefore, for real-time digital signal processing (DSP) systems, special-purpose array processors have become the only appealing alternative. In designing or using such array Processors, most signal processing algorithms share the critical attributes of regularity, recursiveness, and local communication. These properties are effectively exploited in innovative systolic and wavefront array processors. These arrays maximize the strength of very large scale integration (VLSI) in terms of intensive and pipelined computing, and yet circumvent its main limitation on communication. The application domain of such array processors covers a very broad range, including digital filtering, spectrum estimation, adaptive array processing, image/vision processing, and seismic and tomographic signal processing, This article provides a general overview of VLSI array processors and a unified treatment from algorithm, architecture, and application perspectives.
1,249 citations
[...]
11 Jan 1982
TL;DR: Detailed design of the Arithmetic Processor Unit (APU) chip has been completed and all cell types have been run through the design rule check (DRC) programs, corrected and verified.
Abstract: : Detail design of the Arithmetic Processor Unit (APU) chip has been completed. All cell types (100) have been run through the design rule check (DRC) programs, corrected and verified. DRC runs on the entire chip have been run and all corrections have been made. Fifteen out of eighteen of the chip DRC corrections have been verified. The metal, polysilicon and information data layers of the APU layout is shown. The attached drawings, titled 'VLSI Array Processor Arithmetic Processor Unit Chip Plan' is a detail drawing of the APU chip Plan. The functional level simulator of the APU has been built and verified using a set of APU diagnostic code. A gate level logic simulation of the APU has been built. The APU breadboard modules have been fabricated and check out has been initiated. The Array Processor Demonstration System (APDS) modules are in the wire-wrap process. The APDS and APU microcode assembler have been built and checked out. The linker and loader for the APDS have also been built.
46 citations
TL;DR: Real-time signal processing for a 16 channel phased array radar, including space-time adaptive processing (STAP) algorithms, has been implemented using a 29 node ruggedized version of an Intel Paragon, indicating that embedded high performance computers can deliver a significant percentage of their advertised peak throughput under real system constraints.
Abstract: Real-time signal processing for a 16 channel phased array radar, including space-time adaptive processing (STAP) algorithms, has been implemented using a 29 node ruggedized version of an Intel Paragon. Techniques employed to efficiently implement each step of the signal processing are discussed. An overall throughput of 3.15 GFLOPS and processing efficiency of 48% has been achieved, indicating that embedded high performance computers can deliver a significant percentage of their advertised peak throughput under real system constraints.
27 citations
01 Jan 1998
TL;DR: In this paper, real-time signal array radar, including (STAP) algorithms, has 29-node ruggedized version Techniques employed to of the signal processing arc throughput of 3.15 GFLO?S 48% has been achieved, performance computers c;n percentage of their advert system constraints.
Abstract: Real-time signal array radar, including (STAP) algorithms, has 29-node ruggedized version Techniques employed to of the signal processing arc throughput of 3.15 GFLO?S 48% has been achieved, performance computers c;.n percentage of their advert system constraints.
25 citations