Implementation of cryptography algorithm for E-passport security
01 Aug 2016-pp 1-3
TL;DR: This paper shows the comparison of modular multiplication methods used for RSA algorithm for 1024 bit key length using Xilinx ISE 14.3 platform to perform encryption and decryption process targeting Virtex-5 FPGA board.
Abstract: Information Security is a major issue worldwide. Various steps are being taken to improve and upgrade security measures. Border crossings across countries have become one of them. Therefore the use of traditional passports has lead to an improvement in the name of E-passports. E-passports are a more secured and are denoted by a symbol. E-passports contain a small chip which stores the data of passport holder. To protect this data Cryptography is widely used. This paper shows the comparison of modular multiplication methods used for RSA algorithm for 1024 bit key length. Xilinx ISE 14.3 platform is used to perform this encryption and decryption process targeting Virtex-5 FPGA board.
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01 Sep 2017
TL;DR: FPGA implementation of 1024 bit RSA encryption and decryption is presented and QR codes security is demonstrated by deploying AES-RSA hybrid design in Xilinx System Generator(XSG).
Abstract: QR codes, intended for maximum accessibility are widely in use these days and can be scanned readily by mobile phones. Their ease of accessibility makes them vulnerable to attacks and tampering. Certain scenarios require a QR code to be accessed by a group of users only. This is done by making the QR code cryptographically secure with the help of a password (key) for encryption and decryption. Symmetric key algorithms like AES requires the sender and the receiver to have a shared secret key. However, the whole motive of security fails if the shared key is not secure enough. Therefore, in our design we secure the key, which is a grey image using RSA algorithm. In this paper, FPGA implementation of 1024 bit RSA encryption and decryption is presented. For encryption, computation of modular exponentiation for 1024 bit size with accuracy and efficiency is needed and it is carried out by repeated modular multiplication technique. For decryption, L-R binary approach is used which deploys modular multiplication module. Efficiency in our design is achieved in terms of throughput/area ratio as compared to existing implementations. QR codes security is demonstrated by deploying AES-RSA hybrid design in Xilinx System Generator(XSG). XSG helps in hardware co-simulation and reduces the difficulty in structural design. Further, to ensure efficient encryption of the shared key by RSA, histograms of the images of key before and after encryption are generated and analysed for strength of encryption.
6 citations
05 Mar 2021
TL;DR: A high performance, smaller area and low power consumption scalable Systolic-Montgomery-Multiplication based RSA (modulus sizes-1K, 2K and 4K) algorithm targeted for various IoT applications is designed and implemented.
Abstract: Internet-of-things (IoT) is the latest revolution in electronic industry after internet. Smart appliances, portable computing devices, mobile phones and handheld system dominates in IoT, because a large portion of world population use it. Major applications, mainly financial, e-commerce, information security and sensitive data-communication need special attention in terms of security. This creates a strong requirement for providing security solutions into these devices. Incorporating security module inside an Integrated-Circuit(IC) is a major challenge as most of the portable devices are smaller in size and highly power efficient. Hence, an optimized cryptographic implementation techniques, which differ from high-throughput desktop computers and servers need to be developed. RSA algorithm is extensively used public key cryptosystem but it suffers from long execution time. In this paper, we have designed and implemented a high performance, smaller area and low power consumption scalable Systolic-Montgomery-Multiplication based RSA (modulus sizes-1K, 2K and 4K) algorithm targeted for various IoT applications. Huffman compression is used to enhance the execution time. The design is evaluated on Xilinx Artix-7 FPGA. A practical RSA application was run on the design and the performance is superior than X86, ARM, MIPS, NEC and ST architectures. Further the design is integrated with Microblaze processor and we achieved data rate of approximately 56.76 Mbps at 44 MHz operating clock frequency for modular exponentiation operation using dedicated Direct-Memory-Access (DMA).
3 citations
Cites background from "Implementation of cryptography algo..."
...55 4 [18], 1-Kb Virtex-5 - 51 53 5 [19], 1-Kb Virtex-5 54 31 25 6 [20], 32-bits Virtex-5 4 - - 199....
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...The result justifies that our design is power efficient than [18], [19], [20] and [25]....
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01 May 2014
TL;DR: In this paper the design and implementation of 1024 bit-key RSA encryption and decryption module on an FPGA is presented and the module is verified through comparing the result with that obtained from MATLAB tools.
Abstract: Securing the data stored on E-passport is a very important issue. RSA encryption algorithm is suitable for such application with low data size. In this paper the design and implementation of 1024 bit-key RSA encryption and decryption module on an FPGA is presented. The module is verified through comparing the result with that obtained from MATLAB tools. Thedesign runs at a frequency of 36.3 MHz on Virtex-5 Xilinx FPGA. The key size is designed to be 1024-bit to achieve high security for the passport information. The whole design is achieved through VHDL design entry which makes it a portable design and can be directed to any hardware platform.
3 citations
30 Jul 2019
TL;DR: The implementation results in this study were able to work at a maximum frequency of 133.76 MHz, requiring 17.66% LUT (11,195 of 63,400) and 7.14% of IOBs (15 of 210).
Abstract: Lifting and modulus operations are the main operations on the RSA algorithm which require long computation time. Implementation of the operation of the lift and modulus on hardware devices requiring more resources than other arithmetic operations. Montgomery modular multiplication, the method which can be used to simplify the operation of lift and modulus, is implemented on FPGA, to speed up the computing process. The implementation results in this study, which is done using VHDL on the Xilinx Artix 7 series FPGA, were able to work at a maximum frequency of 133.76 MHz, requiring 17.66% LUT (11,195 of 63,400) and 7.14% of IOBs (15 of 210).
1 citations
Cites background or methods from "Implementation of cryptography algo..."
...Some of the methods used to perform arithmetic operations include scanning binary bits from left to right [1], Montgomery Algorithm [4],[5],[6], addition and subtraction with nested loops [3], squares and left to right multiplication [7], and Bit-Serial Systolic [8]....
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...include private key generator operations into the research while other studies do not [7]....
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...[7], as shown in Table 1....
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...using Montgomery parallel [7]....
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23 Feb 2023
TL;DR: In this paper , the authors proposed HyperLedger to secure e-passport management, which in contrast to the public blockchain, is an open-source private blockchain with strong security.
Abstract: To travel globally, a passport is the only official travel document that authenticates the holder's identity and citizenship which is provided by the government. Digital passports provide adamant verification through documentation that tangibly marks the passport owner using biometric techniques because it holds an electronic chip into the passport, also known as an e-passport. The biometric method uses a combination of RFID and fingerprint scanning technology. Notwithstanding, RFID chips have numerous security threats as the information confidentiality can easily be hacked and it is not entirely hassle-free. To get rid of these challenges as a potential remedy, in this paper we propose Hyperledger to secure e-passport management, which in contrast to the public blockchain, is an open-source private blockchain with strong security. When compared to the standard blockchain development framework, the legitimacy of transactions in a private blockchain powered by Hyperledger is substantially distinct, which is enable more effective and quicker transactions while maintaining essential security features. The InterPlanetary File System (IPFS), which has diverse security measures like access control features, non-modifiable data, and immutable history records, and this private ledger have both been used to safeguard private passport information and biometric data.
References
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Book•
01 Jan 2003
TL;DR: In this article, the authors present a survey of the most popular methods for teaching creativity in the field of cryptography and apply them in the context of public-key cryptography and RSA.
Abstract: NOTATION PREFACE CHAPTER 0 READER'S GUIDE CHAPTER 1 OVERVIEW PART ONE SYMMETRIC CIPHERS CHAPTER 2 CLASSICAL ENCRYPTION TECHNIQUES CHAPTER 3 BLOCK CIPHERS AND THE DATA ENCRYPTION STANDARD CHAPTER 4 INTRODUCTION TO FINITE FIELDS CHAPTER 5 ADVANCED ENCRYPTION STANDARD CHAPTER 6 MORE ON SYMMETRIC CIPHERS CHAPTER 7 CONFIDENTIALITY USING SYMMETRIC ENCRYPTION PART TWO PUBLIC-KEY ENCRYPTION AND HASH FUNCTIONS CHAPTER 8 INTRODUCTION TO NUMBER THEORY CHAPTER 9 PUBLIC-KEY CRYPTOGRAPHY AND RSA CHAPTER 10 KEY MANAGEMENT OTHER PUBLIC-KEY CRYPTOSYSTEMS CHAPTER 11 MESSAGE AUTHENTICATION AND HASH FUNCTIONS 1 CHAPTER 12 HASH AND MAC ALGORITHMS CHAPTER 13 DIGITAL SIGNATURES AND AUTHENTICATION PROTOCOLS PART THREE NETWORK SECURITY PRACTICE CHAPTER 14 AUTHENTICATION APPLICATIONS CHAPTER 15 ELECTRONIC MAIL SECURITY CHAPTER 16 IP SECURITY CHAPTER 17 WEB SECURITY PART FOUR SYSTEM SECURITY CHAPTER 18 INTRUDERS CHAPTER 19 MALICIOUS SOFTWARE CHAPTER 20 FIREWALLS APPENDICES APPENDIX A STANDARDS AND STANDARD-SETTING ORGANIZATIONS APPENDIX B PROJECTS FOR TEACHING CRYPTOGRAPHY AND NETWORK SECURITY ONLINE APPENDICES APPENDIX C SIMPLIFIED DES APPENDIX D THE MEANING OF mod APPENDIX E MORE ON SIMPLIFIED AES APPENDIX F KNAPSACK PUBLIC-KEY ALGORITHM APPENDIX G PROOF OF THE DIGITAL SIGNATURE ALGORITHM GLOSSARY REFERENCES INDEX LIST OF ACRONYMS
1,569 citations
Book•
01 Mar 2015
901 citations
"Implementation of cryptography algo..." refers methods in this paper
...The pseudo code is as shown [3]: Input: A, B, n Output : E = A mod n E <= 1; for i = k-1 to 0 if Bi = 1 E <= A*E mod n; end if if i >0 E <= E*E mod n; end if end for return E;...
[...]
Book•
14 Jan 2009
TL;DR: Hardware Implementation of Finite-Field Arithmetic describes algorithms and circuits for executing finite-field operations, including addition, subtraction, multiplication, squaring, exponentiation, and division.
Abstract: Implement Finite-Field Arithmetic in Specific Hardware (FPGA and ASIC)
Master cutting-edge electronic circuit synthesis and design with help from this detailed guide. Hardware Implementation of Finite-Field Arithmetic describes algorithms and circuits for executing finite-field operations, including addition, subtraction, multiplication, squaring, exponentiation, and division.
This comprehensive resource begins with an overview of mathematics, covering algebra, number theory, finite fields, and cryptography. The book then presents algorithms which can be executed and verified with actual input data. Logic schemes and VHDL models are described in such a way that the corresponding circuits can be easily simulated and synthesized. The book concludes with a real-world example of a finite-field application--elliptic-curve cryptography. This is an essential guide for hardware engineers involved in the development of embedded systems.
Get detailed coverage of:
Modulo m reduction
Modulo m addition, subtraction, multiplication, and exponentiation
Operations over GF(p) and GF(pm)
Operations over the commutative ring Zp[x]/f(x)
Operations over the binary field GF(2m) using normal, polynomial, dual, and triangular
Table of contents
Chapter 1. Mathematical background
Chapter 2. Mod m reduction
Chapter 3. Mod m operations
Chapter 4. Operations over GF(p)
Chapter 5. Operations over Zp [x] / f(x)
Chapter 6. Operations over GF(pn)
Chapter 7. Operations over GF(2m) - Polynomial bases
Chapter 8. Operations over GF(2m) - Normal bases
Chapter 9. Operations over GF(2m) - Other bases
Chapter 10. Elliptic curve cryptographyAppendix A. p = 2(192) - 2(64) - 1
Appendix B. Optical Extension Fields
Appendix C. Binary Fields
Appendix D. Ada versus VHDL
Index
107 citations
"Implementation of cryptography algo..." refers methods in this paper
...Montgomery algorithm [5] using single carry save adder for modular multiplication is preferred....
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01 Dec 2014
TL;DR: The paper analyses the study of various technologies used in Epassport design and describes privacy and security issues that apply to e-passports, and analyzes these issues in the context of the International Civil Aviation Organization (ICAO) standard for e- passports.
Abstract: In last few years' terrorist and illegal attacks across many country borders has increased which led to security and strict passport verification process. This turned down legitimate travelers. Many countries are in process of implementing electronic passports to travelers for travelling, automating passport verification process and increasing border security. The e-passport deploys two popular technologies: Radio frequency Identification (RFID) and Biometrics. Personal credentials and bearers biometric data is stored on RFID chip which is used in verification process by border security officers. The next generation of e-passports will implement more advanced cryptographic mechanisms, collectively known as Extended Access Control, and in particular a protocol referred to as Chip Authentication that protects an e-passport against cloning and transferability attacks. The Extended Access Control suite of protocols has found minor attention in the literature until now. The paper analyses the study of various technologies used in Epassport design. A cryptographic security analysis of the epassport using face fingerprint, palm print and iris biometric that are intended to provide improved security in protecting biometric information of the e-passport bearer. Together, RFID and biometric technologies promise to reduce fraud, ease identity checks, and enhance security. At the same time, these technologies raise new risks. We explore the privacy and security implications of this worldwide implementing next-generation authentication technology: e-passport. We describe privacy and security issues that apply to e-passports, and then analyze these issues in the context of the International Civil Aviation Organization (ICAO) standard for e-passports.
22 citations
Journal Article•
03 Jan 2014-World Academy of Science, Engineering and Technology, International Journal of Computer, Electrical, Automation, Control and Information Engineering
TL;DR: In this article, the design and implementation of 1024 bit-key RSA encryption and decryption module on an FPGA is presented and verified through comparing the result with that obtained from MATLAB tools.
Abstract: Securing the data stored on E-passport is a very important issue. RSA encryption algorithm is suitable for such application with low data size. In this paper the design and implementation of 1024 bit-key RSA encryption and decryption module on an FPGA is presented. The module is verified through comparing the result with that obtained from MATLAB tools. Thedesign runs at a frequency of 36.3 MHz on Virtex-5 Xilinx FPGA. The key size is designed to be 1024-bit to achieve high security for the passport information. The whole design is achieved through VHDL design entry which makes it a portable design and can be directed to any hardware platform.
4 citations