Implementation of fault simulation and testing of combinational circuits
01 May 1989-International Journal of Electronics (Taylor & Francis Group)-Vol. 66, Iss: 5, pp 665-678
TL;DR: A software implementation of a logic simulator capable of testing combinational circuits is presented, capable of handling both single and multiple faults.
Abstract: A software implementation of a logic simulator capable of testing combinational circuits is presented. Exhaustive testing methodologies like syndrome and index vector testing are applied to make the testing procedure simpler. However, a-tests and b-tests have to be generated and applied in the case of index vector untestable circuits. The method is capable of handling both single and multiple faults. Sample runs have also been included.
References
More filters
Book•
01 Jan 2010TL;DR: Theories are made easier to understand with 200 illustrative examples, and students can test their understanding with over 350 end-of-chapter review questions.
Abstract: Understand the structure, behavior, and limitations of logic machines with this thoroughly updated third edition. Many new topics are included, such as CMOS gates, logic synthesis, logic design for emerging nanotechnologies, digital system testing, and asynchronous circuit design, to bring students up-to-speed with modern developments. The intuitive examples and minimal formalism of the previous edition are retained, giving students a text that is logical and easy to follow, yet rigorous. Kohavi and Jha begin with the basics, and then cover combinational logic design and testing, before moving on to more advanced topics in finite-state machine design and testing. Theory is made easier to understand with 200 illustrative examples, and students can test their understanding with over 350 end-of-chapter review questions.
1,315 citations
IBM1
TL;DR: This paper focuses on classical testing of combinational circuits and the large storage requirement for a list of the fault-free response of the circuit to the test set.
Abstract: Classical testing of combinational circuits requires a list of the fault-free response of the circuit to the test set. For most practical circuits implemented today the large storage requirement for such a list makes such a test procedure very expensive. Moreover, the computational cost to generate the test set increases exponentially with the circuit size.
219 citations
TL;DR: Testing of logic networks by verifying the Walsh coefricients of the outputs is explored, and measurement of one of these can detect arbitrarily many input leads stuck, and just two measurements can detect any single stuck-at fault in appropriately designed networks.
Abstract: Testing of logic networks by verifying the Walsh coefricients of the outputs is explored. Measurement of one of these can detect arbitrarily many input leads stuck, and just two measurements, requiring little hardware, can detect any single stuck-at fault in appropriately designed networks.
109 citations
TL;DR: It is shown that the enumeration of errors missed by ACT for a unit under test is equivalent to the number of restricted partitions of a number, which indicates that with ACT a better control over fault coverage can be obtained.
Abstract: A new test data reduction technique called accumulator compression testng (ACT) is proposed ACT is an extension of syndrome testing It is shown that the enumeration of errors missed by ACT for a unit under test is equivalent to the number of restricted partitions of a number Asymptotic results are obtained for independent and dependent error modes Comparison is made between signature analysis (SA) and ACT Theoretical results indicate that with ACT a better control over fault coverage can be obtained than with SA Experimental results are supportive of this indication Built-in self test for processor environments may be feasible with ACT However, for general VLSI circuits the complexity of ACT may be a problem as an adder is necessary
61 citations
26 citations