Implementation of Hierarchical DFT Approach for Better Testability
11 Jul 2018-pp 1-4
TL;DR: This paper presents an implementation of Hierarchical DFT approach to get better testability i.e. more test coverage at block level and logical simulation for the proper top mapping connections.
Abstract: This paper presents an implementation of Hierarchical DFT approach to get better testability i.e. more test coverage at block level. The SOC is divided into number of Layout regions and layout as well as DFT regions as per the functionality requirement. The well-proven D-algorithm technique is considered for ATPG purpose. The Vectors are generated at the DF level inside the chip using Modus tool from Cadence at 16nm technology. For DFT region in the SOC, patterns are targeted for different test modes which includes both stuck-at and transition fault coverage. Each and every DFT region is targeted for Stuck-at and transition fault coverage of greater than 99% and 85% respectively. Before applying these patterns on the real silicon (chip) in the ATE (Automatic Test Equipment), they are validated by Simulation using IES from cadence at both block and device level. At block level the patterns are validated with and without timing constraints. The timing constrained simulation occurs by annotating the design netlist w.r.t. STA related timing reports, called as SDC constraints. Further, the block level DFT region pins are mapped to the corresponding device level pins. The patterns generated at block level being mapped to device level are again validated by logical simulation for the proper top mapping connections.
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26 Oct 2004
TL;DR: Case study information on ATPG- and DFT-based solutions for test power reduction is presented and ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test.
Abstract: It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically increasing pattern volume for a given coverage. We present case study information on ATPG- and DFT-based solutions for test power reduction.
285 citations
18 Oct 1998
TL;DR: The design of scan chains as transport mechanism for test patterns from IC pins to embedded cores and vice versa and the test time consequences of reusing cores with fixed internal scan chains in multiple ICs with varying design parameters are analyzed.
Abstract: The size of the test vector set forms a significant factor in the overall production costs of ICs, as it defines the test application time and the required pin memory size of the test equipment. Large core-based ICs often require a very large test vector set for a high test coverage. This paper deals with the design of scan chains as transport mechanism for test patterns from IC pins to embedded cores and vice versa. The number of pins available to accommodate scan test is given, as well as the number of scan test patterns and scannable flip flops of each core. We present and analyze three scan chain architectures for core-based ICs, which aim at a minimum test vector set size. We give experimental results of the three architectures for an industrial IC. Furthermore we analyze the test time consequences of reusing cores with fixed internal scan chains in multiple ICs with varying design parameters.
216 citations
"Implementation of Hierarchical DFT ..." refers background or methods in this paper
...Design For Testability (DFT) is a methodology that gives structural way of test pattern generation and diagnosis easier [1]....
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...SoC (device level) design focuses on integration of small layout and DFT regions, hierarchical solutions are naturally suited for all design steps, DFT being no exception [1]....
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06 Jan 2007
TL;DR: This paper takes up the challenge of reducing the overhead of daisy mode in divide-and-conquer testing by a careful analysis of the interactions between partitions, and introduces additional test modes to increase the coverage of glue logic by making sure that the number of scan cells involved in these "intermediate daisy modes" are minimal.
Abstract: A hierarchical or "divide-and-conquer" scan test methodology enables us to partition a large SoC into several partitions and perform design-for-testability (DFT) functions such as scan insertion, pattern generation, and pattern validation separately on individual partitions. Since the effort for DFT related tasks grows super-linearly with gate count, partitioning reduces the effort for DFT tasks. Further, test application can be divided into k + 1 modes, where k modes correspond to independent testing of the partitions and the (k + 1)th mode corresponds to a "residual" (or daisy) mode where faults that are not covered by the individual modes are considered. In reality, however, the daisy mode can be a killer and wipe out the benefits of divide-and-conquer testing. This is especially true for partitions that do not have test wrappers. In this paper, we take up the challenge of reducing the overhead of daisy mode in divide-and-conquer testing. By a careful analysis of the interactions between partitions, additional test modes are introduced to increase the coverage of glue logic, at the same time making sure that the number of scan cells involved in these "intermediate daisy modes" are minimal. We refer to this version of hierarchical scan testing as "quiet and optimized divide-and-conquer scan". Experimental results reveal that the proposed technique reduces the test time overhead of the conventional daisy mode by about 20times. In addition, the technique drastically reduces the switching activity in the daisy modes and hence reduces the test power
17 citations
"Implementation of Hierarchical DFT ..." refers methods in this paper
...Using hierarchical DFT approach having various advantages like test vectors can be reduced using the compression technique, reduction in test power by controlling the switching activity of the scan flip-flops between the two consecutive vectors [5]....
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11 May 2016
TL;DR: A tool set for teaching and e-learning the main principles of design-for-testability technics for digital systems, a collection of software tools which simulate a circuit under test, emulate a pool of different strategies, methods and algorithms of self-testing and improve testability of the exercised circuit.
Abstract: We propose a tool set for teaching and e-learning the main principles of design-for-testability technics for digital systems. It is a collection of software tools which simulate a circuit under test, emulate a pool of different strategies, methods and algorithms of self-testing and improve testability of the exercised circuit. The tools support university courses on digital electronics, testing of digital systems, design for test to learn by hands-on exercises how to design digital systems, how to make them testable, how to build self-testing systems, how to generate test patterns, how to analyze the quality of tests and how to assure the required quality by improving the testability. General ideas of organization of hands-on laboratory research are outlined. The research tasks are set up in a way that involves a competition between students, and as a consequence, motivates them to better understand the problem, and to look for best strategies of design-for-testability.
1 citations
"Implementation of Hierarchical DFT ..." refers background in this paper
...We often standup across the unwrapped cores in the actual design as that would either lead to reluctance of the RTL designer to insert extra DFT logic at wrapper level because that results in either area or performance overhead [4]....
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